Preparation method of semiconductor device

Abstract

The invention relates to a preparation method of a semiconductor device. The method comprises: providing a semiconductor substrate; forming a virtual gate on the semiconductor substrate; forming a first offset side wall and a second offset side wall at the side of the virtual gate; removing the virtual gate; and removing the first offset side wall to form a groove with the increased critical dimension. According to the invention, after the virtual gate is formed, a thermal treatment oxide layer, the first offset side wall, and the second offset side wall are formed on the virtual gate; and after LDD and source-drain ion injection are executed, the thermal treatment oxide layer and the first offset side wall are removed to form the groove, wherein the critical dimension of the groove is the critical dimension of the metal gate and the critical dimension of the metal gate is larger than that of the conventional metal gate. Moreover, the thermal treatment oxide layer and the first offset side wall are formed after the source-drain ion injection, so that the large critical dimension is obtained and the shadow effect can be avoided and thus the device performance is improved.

Description

technical field [0001] The invention relates to a semiconductor device technology, in particular, the invention relates to a method for preparing a semiconductor device. Background technique [0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. At present, since the semiconductor industry has advanced to the nanotechnology process node in the pursuit of high device density, high performance and low cost, especially when the size of semiconductor devices is reduced to 20nm or below, the fabrication of semiconductor devices is limited by various physical limits. [0003] When the size of a semiconductor device is reduced to 20nm or below, the gate critical dimension (gate CD) in the device is correspondingly reduced to 24nm. With the reduction of technology nodes, the traditional gate dielectric layer cont...

AI Technical Summary

Problems solved by technology

[0005] Compared with the gate first process (gate first), in the "gate last (high-K&gate last)" process, not only the metal is filled in the trench, but also the high-K dielectric and covering layer (cap layer), so the filling of the void after etching and removing the dummy gate in the gate-last (high-K&gate last) process becomes a key issue. In the prior art, in order to improve the filling of the void in the gate-last (high-K&gate last) process, The method of increasing the critical dimension of the dummy gate is usually adopted. When the critical dimension of the dummy gate

Images