Method for forming gate structure of NAND memory, NAND memory and photomask

Abstract

The invention relates to a gate structure forming method of an NAND memory, a NAND memory and a photomask, and relates to a semiconductor integrated circuit manufacturing process. The method comprisesthe steps of in the forming process of the gate structure of the NAND memory, forming a mandrel pattern shape for forming a control gate structure through a first photoetching exposure process, and forming a mandrel pattern morphology used for forming a peripheral gate structure and a selection gate structure; then, in the process of removing the mandrel pattern structure through a second photoetching exposure process, protecting an area for forming the peripheral gate and selection gate structures by using photoresist so as to remove the control gate mandrel film layer; in the subsequent etching of the gate structure, forming the control gate by the remaining side walls; and forming the peripheral gate and the selection gate by the side walls and the unremoved mandrel pattern structure together. The critical size of the side wall used for forming the outermost periphery of the control gate is not large, and the influence of interlayer registration deviation on the subsequent processis weakened.

Description

technical field [0001] The invention relates to a manufacturing process of a semiconductor integrated circuit, in particular to a gate structure forming method of a NAND memory, a NAND memory and a photomask mask. Background technique [0002] In semiconductor integrated circuits, NAND memory (NAND flash) is a non-volatile memory. Due to its large capacity, fast erasing and writing speed, and low cost, it is suitable for data storage and is widely used in consumer, automotive, and industrial electronics. and other fields. [0003] see figure 1 , figure 1 It is a schematic diagram of the architecture of NAND memory, such as figure 1 As shown, a NAND memory is usually composed of a storage area and a peripheral area. The peripheral area is composed of a plurality of peripheral tubes. The storage area is further composed of a plurality of blocks. Each block consists of two selector tubes and several control tubes. The selection tubes are located at both ends of the block...

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to provide a method for forming a gate structure of NAND memory, to solve the problem of load effect during sidewall etching and to weaken the impact of interlayer registration deviation on subsequent processes

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