A kind of formation method of high-k metal gate

Abstract

The invention provides a forming method of a high-K metal grid. The method comprises the following steps of step 1: sequentially forming an interlayer dielectric layer, a TiO2 film layer and a polycrystalline silicon layer on a substrate; step 2: performing patterning on the interlayer dielectric layer, the TiO2 film layer and the polycrystalline silicon layer so as to form a pseudo grid electrode structure; forming a grid electrode side wall at the side edge of the pseudo grid electrode structure; step 3: depositing the interlayer electric dielectric materials on the periphery of the pseudo grid electrode structure; flattening the interlayer electric dielectric materials; step 4: removing the top polycrystalline silicon layer in the pseudo grid electrode structure to form a groove; step 5: performing Hf ion injection on the TiO2 film layer in the pseudo grid electrode structure so as to form an HfTiO film layer; step 6: filling metal materials into the groove so as to form the metal grid.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, and more specifically, the invention relates to a method for forming a high-K (high dielectric constant) metal gate. Background technique [0002] Traditionally, the growth of the high-K film and the metal gate are placed in the process integration after the active area activation thermal anneal process (S / D active anneal), and the dummy gate polysilicon and dummy gate oxide are finally removed. . In the process of removing the dummy gate oxide, the surface roughness of the channel will become larger. At the same time, during the etching process, whether it is dry etching or wet etching, harmful substances such as F ions will be introduced. Impurity ions. These ions diffuse into the channel, severely affecting the reliability of the device. At the same time, a high-K film will be deposited on the sidewall, and the gap that can be filled by the gate will be reduced by almost 4nm, whic...

AI Technical Summary

Problems solved by technology

In the process of removing the dummy gate oxide, the surface roughness of the channel will become larger. At the same time, during the etching process, whether it is dry etching or wet etching, harmful substances such as F ions will be introduced. Impurity ions

These ions diffuse into the channel and have a severe impact on the reliability of the device

At the same time, a high-K film will be deposited on the sidewall, and the gap that can be filled by the gate will be reduced by almost 4nm, which greatly increases the risk of metal voids.

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