Radiation hardened high-performance DICE latch

Abstract

The invention discloses a radiation hardened high-performance DICE latch. Four PMOS transistors are added on the basis of a traditional DICE latch, and a source isolation technology is used for improving the multi-node upset resistant capacity of the latch. Compared with the MDICE latch structure, the area, delay and power consumption are all reduced, and particularly the delay is greatly reducedwhen 1 is storing. Compared with the other hardened structures, the radiation hardened high-performance DICE latch compromises with the area, delay and power consumption while improving the multi-nodeupset resistant capacity.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a unit circuit structure that can increase storage speed, reduce latch power consumption and improve the ability of the latch to resist single-event multi-node flipping, and is a storage unit based on double interlocking (Dualinterlocked storage cell, DICE) radiation-hardened high-performance DICE latches. Background technique [0002] With the reduction of feature size and power supply voltage, the circuit is more and more sensitive to radiation, and the single event effect (Single-Event Effect, SEE) becomes an inevitable problem, which makes the development of SEE radiation hardening technology in combinational circuits very urgent. Single-Event Upset (SEU) is a form of SEE that is soft and non-destructive. When heavy ion particles are incident on semiconductor materials, excess charges will be ionized, and these excess charges will be collected by device electrodes, c...

AI Technical Summary

Problems solved by technology

The simulation results show that the structure has a good ability to resist multi-node flipping, which is improved compared with the traditional DICE structure, but its power consumption is large

In addition, the structure has a large delay when storing data '1'

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