Testing device based on DDR
A test device and test data technology, applied in electronic circuit testing and other directions, can solve the problems of high power, difficult miniaturization, and high manufacturing costs, and achieve the effects of reducing power consumption, improving performance and integration, and reducing line power consumption
Pending Publication Date: 2018-07-27
SHENZHEN AID TECH
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Problems solved by technology
It aims to solve the problems of excessive power, difficulty in miniaturization, and high manufacturing cost of existing integrated circuit testing equipment
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[0027] The present invention provides a test device based on FPGA. In order to make the objectives, technical solutions and effects of the present invention clearer and clearer, the present invention will be described in further detail below. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.
[0028] The normal application of FPGA (Field-Programmable Gate Array) is to install it on a fixed circuit board, and the circuit components connected to it are fixed. The input and output standards and modes of the FPGA are set according to the performance standards of the connected components, and are not required and will not be changed at any time.
[0029] The present invention utilizes FPGA whose circuit can be changed according to the requirements of different tested components, and its wiring, input and output standards, time delay and mode can be set to the corresponding standa...
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The invention discloses a testing device based on DDR. The corresponding testing device is innovatively designed by means of an FPGA circuit and the adjustability of an output and input standard and mode, and a corresponding electronic circuit of an existing measuring device is replaced. Performance is greatly improved, and meanwhile the circuit power consumption, key design physical size and costare greatly reduced. In addition, a large amount of test data is innovatively transmitted to a device directly connected with a tested element at a high speed by means of the high-speed data transmission performance of an FPGA, and one of bottle necks of key design miniaturization is solved. Furthermore, a DC related circuit for low-speed performance testing and a high-speed testing circuit are completely separated and only connected with the tested element during testing so that the two circuits cannot be influenced by each other and can also be connected together when needing to be connected together for corresponding testing. Thus, the power consumption, physical size and cost are greatly reduced, and quite good market application and popularization prospects are realized.
Description
Technical field [0001] The invention relates to the technical field of electronic testing, and more specifically, to a DDR-based testing device. Background technique [0002] The integrated circuit test equipment includes a circuit for driving the component under test and receiving the output signal of the component under test. In the prior art, it is realized by specially designed special electronic devices. It has the following disadvantages: [0003] 1. Because it is specially designed and manufactured for this purpose, its consumption is small, so the design and manufacturing cost is extremely high; [0004] 2. Because its driving and receiving voltage is continuously controllable, it is very difficult to achieve high speed, and because of the high power consumption, it cannot be miniaturized due to heat dissipation problems. [0005] In addition, the controllable delay circuit used to adjust the timing of each channel in the prior art is a split element, which also makes miniat...
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IPC IPC(8): G01R31/28
Inventor 陆放
Owner SHENZHEN AID TECH