High-density 3D vertical RERAM with bidirectional threshold-type selector

Abstract

The present disclosure, in various embodiments, describes three-dimensional (3D) vertical resistive random access memory (ReRAM) structures. In one embodiment, a memory device includes a resistive memory element and a selector coupled in series with the resistive memory element. A turn-on voltage of the selector is greater than a bias voltage of the memory device in an unselected state such that the selector remains in a turn-off state when the memory device is unselected, and the selector is configured to have substantially the same resistance in both a forward bias direction and a reverse bias direction in a turn-on state.

Description

[0001] This application claims priority and benefit to U.S. Provisional Application Serial No. 62 / 449,528, filed January 23, 2017, entitled "High Density 3D Vertical RERAM with Bidirectional Threshold-Type Selector," the entire contents of which Incorporated herein by reference. technical field [0002] In various embodiments, the present disclosure relates to vertical memory structures, and more particularly to three-dimensional (3D) vertical resistive random access memory (ReRAM) structures. Background technique [0003] In a variety of consumer electronics and computers, solid-state data storage devices incorporating non-volatile memory (NVM) often replace or supplement conventional spinning hard drives for mass storage. Some memory architectures, such as one-transistor-one-resistor (1T1R) architectures, may be relatively easy to implement, may have little or no disturb effects or sneak paths, and / or may have high parallelism, but may have large footprint, which creates ...

AI Technical Summary

Problems solved by technology

Some memory architectures, such as one-transistor-one-resistor (1T1R) architectures, may be relatively easy to implement, may have little or no disturb effects or sneak paths, and / or may have high parallelism, but may have large footprint, which creates scalability difficulties

Such memory architectures may also be difficult or impossible to stack for increased storage density, resulting in higher cost, lower storage density

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