PCIe link elastic buffer circuit

Abstract

The invention provides a PCIe link elastic buffer circuit. The circuit comprises a write data and data label generation module (1), a write pointer control module (2), a write depth calculation module(3), an elastic buffer memory (4), a read data and data label generation module (5), a read pointer control module (6), a read depth calculation module (7), a 8B / 10B decoding module (8) and a reception state generation module (9). Through the circuit, empty and full states of PCIe link received data buffers are automatically detected, SKIP ordered sets are added and deleted, an elastic write operation and an elastic read operation of data of each reception channel at PCIe port reception ends are managed, frequency accumulation deviations between write clocks and read clocks of link data reception buffers are corrected, accurate matching of data transmission speed between transmission ports and reception ports is completed, data damage and loss caused by overflow and underflow of receptionbuffers are prevented, integrity of received data is ensured, and high-speed and high-reliability transmission of PCIe link data is realized.

Description

technical field [0001] The invention belongs to the technical field of computers, and in particular designs a PCIe link elastic buffer circuit. Background technique [0002] The serial PCIe interface has the characteristics of high speed and high bandwidth, overcomes the inherent defects of the traditional PCI bus in terms of system bandwidth and transmission speed, and has a good application prospect. [0003] The accuracy of the clock circuits on both sides of the PCIe link is ±300ppm, that is, a deviation of ±300 clock cycles is allowed within the time range of every million and ideal clock cycles. Worst case, if the transmitter on one side of the link operates at 2.5GHz + 300ppm, and the receiver on the other side of the link has a local clock running at 2.5GHz-300ppm, there is a maximum deviation of 600ppm, accumulating 10 -6 / 600=1667 clock cycles, which will generate a clock cycle offset. [0004] For the continuous data stream of high-speed transmission, it is used...

AI Technical Summary

Problems solved by technology

[0004] For the continuous data stream of high-speed transmission, it is used for cross-clock processing and buffer for receiving data. The write clock of data comes from the clock of the sending end recovered from the received data, and the read clock comes from the clock generated by the local crystal oscillator of the receiving end. If the cumulative clock cycle skew between the write clock and the read clock cannot be handled correctly, it will cause overflow of the data receiving buffer, damage the received data or cause data loss, seriously affecting the function and performance of the system communication

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