pcie link elastic buffer circuit

Abstract

The invention provides a PCIe link elastic buffer circuit, comprising: write data and data flag generation module (1), write pointer control module (2), write depth calculation module (3), elastic buffer memory (4), Read data and data sign generation module (5), read pointer control module (6), read depth calculation module (7), 8B / 10B decoding module (8), receiving state generation module (9). The invention automatically detects the empty and full state of the receiving data buffer of the PCIe link through the circuit, adds and deletes the SKIP ordered set, manages the elastic writing and elastic reading operation of each receiving channel data at the receiving end of the PCIe port, and corrects the link data The cumulative frequency deviation between the write clock and the read clock of the receiving buffer completes the precise matching of the data transmission rate of the sending and receiving ports, prevents data damage and loss caused by the overflow and underflow of the receiving buffer, and ensures the integrity of the received data , to achieve high-speed and highly reliable transmission of PCIe link data.

Description

technical field [0001] The invention belongs to the technical field of computers, in particular to a PCIe link elastic buffer circuit. Background technique [0002] The serial PCIe interface has the characteristics of high speed and high bandwidth, overcomes the inherent defects of the traditional PCI bus in terms of system bandwidth and transmission speed, and has a good application prospect. [0003] The accuracy of the clock circuits on both sides of the PCIe link is ±300ppm, that is, a deviation of ±300 clock cycles is allowed within the time range of every million and ideal clock cycles. In the worst case, if the transmitter on one side of the link operates at 2.5GHz + 300ppm, and the local clock of the receiver on the other side of the link operates at 2.5GHz - 300ppm, there is a maximum deviation of 600ppm, accumulating 10 －6 / 600=1667 clock cycles, which will generate a clock cycle offset. [0004] For the continuous data stream of high-speed transmission, it is us...

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Problems solved by technology

[0004] For the continuous data stream of high-speed transmission, it is used for cross-clock processing and buffer for receiving data. The write clock of data comes from the clock of the sending end recovered from the received data, and the read clock comes from the clock generated by the local crystal oscillator of the receiving end. If the cumulative clock cycle skew between the write clock and the read clock cannot be handled correctly, it will cause overflow of the data receiving buffer, damage the received data or cause data loss, seriously affecting the function and performance of the system communication

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