Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the following steps of: forming a first through hole that penetrates through a dielectric layer and exposes a surface of a source-drain doping region; forming a second through hole that penetrates through the dielectric layer and exposes a top of a gate structure; depositing cap layers on abottom and sidewalls of the first through hole and a bottom and sidewalls of the second through hole; performing a first cleaning process on the bottom of the first through hole and the bottom of thesecond through hole to remove cap layers located on the bottom of the first through hole and the bottom of the second through hole; performing a second cleaning process on the source-drain doping region exposed at the bottom of the first through hole and the gate structure exposed at the bottom of the second through hole after the first cleaning process; forming metal layers on the bottom and thesidewalls of the first through hole, the bottom and the sidewalls of the second through hole and a top of the dielectric layer after the second cleaning process; and performing an annealing process on the metal layers to convert the metal layer located on the source-drain doping region into a metal silicide layer. According to the invention, the electrical properties of the formed semiconductor structure can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] As the production of integrated circuits develops towards ultra-large-scale integrated circuits, the circuit density inside integrated circuits is increasing, and the number of components contained is also increasing, making it difficult for the surface of the wafer to provide enough area to manufacture the required interconnections. connection. [0003] In order to meet the requirements of the interconnection line after the size of the component is reduced, the design of the interconnection metal layer has become a method usually adopted in the VLSI technology. At present, the conduction between the interconnected metal layers is realized through conductive plugs, and the conduction between the interconnected metal layers and the semiconductor structure is also realized thr...

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Problems solved by technology

[0004] However, the electrical performance of the semiconductor structure with conductive plugs formed by the prior art needs to be improved

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