Accelerating circuit of 3*3 convolution algorithm

A technology for accelerating circuits and convolution operations, applied in image memory management, processor architecture/configuration, etc., can solve the problems of consuming software instructions, inefficiency, and occupying software resources, so as to save bandwidth, reduce time consumption, and process image complete effect

Pending Publication Date: 2018-10-19
AMICRO SEMICON CORP
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Problems solved by technology

However, the convolution algorithm requires software to read in, cache, calculate, and then write out the image dat

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  • Accelerating circuit of 3*3 convolution algorithm
  • Accelerating circuit of 3*3 convolution algorithm
  • Accelerating circuit of 3*3 convolution algorithm

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[0021] The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings:

[0022] The concept of the invention is: in the process of traversing the input source image, the window of the 3*3 convolution kernel stores the pixels from the input source image stored in the DDR or SRAM through three single-port 1KB line buffer SRAM buffers, and uses the state machine to store the pixels of the input source image. and the column address count value to realize the sliding of the center pixel of this window in the input source image to complete the matrix convolution operation, then write the result of the convolution operation into the 16-layer 8-bit FIFO, and finally use the AHB bus to transfer the data in the FIFO Write back the DDR and send an interrupt to the CPU, enabling hardware-accelerated convolution calculations.

[0023] Based on the above inventive concept, an embodiment of the present invention provides an acc...

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Abstract

The invention discloses an accelerating circuit of a 3*3 convolution algorithm, comprising a DDR module, a convolution result FIFO module, a main state machine control module, a shift selection control module, a row buffer module and a convolution calculation module. A main control module performs burst read on pixel data of current two adjacent rows of an input image from a pixel storage array through an AHB bus interface, controls the parallel shift of the pixel data in the shift selection control module so that the pixel data written in the convolution calculation module each time and the corresponding convolution kernel data are subjected to convolution operation, writes an operation result of the pixel data of the current two adjacent rows in the convolution calculation module into aconvolution result storage array through an AHB bus, then, reads the pixel data of the next row through the AHB bus, performs corresponding shift and convolution operations until all pixel data of theinput image are processed, and sends an interrupt to inform the CPU of a result of convolution operation processing so as to reduce the software instruction overhead.

Description

technical field [0001] The invention relates to the technical field of machine vision detection, in particular to an acceleration circuit of a 3*3 convolution algorithm. Background technique [0002] At present, when the sweeper uses video images for map construction and positioning, it needs to preprocess the image data collected by the camera through a set of image processing algorithms, such as image filtering, image noise removal, image feature enhancement, image Smoothing, etc. [0003] In the field of existing machine vision technology, window processing is a common processing in image processing. Commonly used window processing includes morphological operations, blur filtering, Gaussian filtering, etc. Among them, the convolution algorithm is widely used. However, the convolution algorithm requires software to read in, cache, calculate, and then write out the image data, which consumes a lot of software instructions and occupies a lot of software resources, resulti...

Claims

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Application Information

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IPC IPC(8): G06T1/20G06T1/60
CPCG06T1/20G06T1/60Y02D10/00
Inventor 何再生
Owner AMICRO SEMICON CORP
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