Accelerating circuit of 3*3 convolution algorithm
A technology for accelerating circuits and convolution operations, applied in image memory management, processor architecture/configuration, etc., can solve the problems of consuming software instructions, inefficiency, and occupying software resources, so as to save bandwidth, reduce time consumption, and process image complete effect
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[0021] The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings:
[0022] The concept of the invention is: in the process of traversing the input source image, the window of the 3*3 convolution kernel stores the pixels from the input source image stored in the DDR or SRAM through three single-port 1KB line buffer SRAM buffers, and uses the state machine to store the pixels of the input source image. and the column address count value to realize the sliding of the center pixel of this window in the input source image to complete the matrix convolution operation, then write the result of the convolution operation into the 16-layer 8-bit FIFO, and finally use the AHB bus to transfer the data in the FIFO Write back the DDR and send an interrupt to the CPU, enabling hardware-accelerated convolution calculations.
[0023] Based on the above inventive concept, an embodiment of the present invention provides an acc...
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