A BCH code based ECC system and a memory

Abstract

The invention discloses a BCH code based ECC system and a memory. The ECC system comprises a BCH decoder and an error correcting capability control circuit. The BCH decoder comprises a plurality of operation units. The error correcting capability control circuit is used for controlling the operation state of the operation units in the BCH decoder according to an error rate of to-be-decoded data tochange the error correcting capability of the BCH decoder. The ECC system controls the operation state of the operation units in the BCH decoder according to the error rate of the to-be-decoded datathrough the error correcting capability control circuit, that is to say, the number of circuits when the BCH decoder is running is changed, so that a corresponding error correcting ability can still be achieved when only part of the circuits are running at a low error rate and the power consumption can be greatly reduced at the same time.

Description

technical field [0001] The present invention relates to the technical field of memory, and more specifically, relates to an ECC system and memory based on BCH codes. Background technique [0002] With the continuous development of science and technology, various memories have been widely used in people's daily life and work, bringing great convenience to people's life. [0003] Based on the "big data" era, high-capacity and low-power memory is developing rapidly. Since 3D NAND flash memory entered the market in 2014, the capacity of flash memory has almost doubled every year. As the storage capacity increases, the complexity and power consumption of the ECC (Error Correcting Code, error checking and correction) system also increase, and the power consumption mainly comes from the ECC module. [0004] Since the data bit error rate is relatively low at the beginning of the use of the memory chip, the working efficiency of the ECC module in the memory chip is very low at this ...

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Problems solved by technology

[0004] Since the bit error rate of the data is relatively low at the beginning of the use of the memory chip, the working efficiency of the ECC module in the memory chip is very low at this time, and the bit error rate of the data is a very slow rising process, that is to say, the ECC module will be in an unstable state for a long time. In the saturated working state, the error correction capability of the traditional ECC module is fixed and there is a lot of redundant power consumption when the circuit is running. The power consumption for data with different bit error rates is basically the same, and a large amount of power consumption will be wasted. Lose

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