Low-power-consumption phase-locked loop frequency synthesizer

Abstract

The invention discloses a low-power-consumption phase-locked loop frequency synthesizer, comprising a frequency rough tuning loop, a frequency fine tuning loop, an annular oscillator and a tuning varactor; the tuning varactor is provided with a first tuning terminal and a second tuning terminal, the first tuning terminal is connected with an output node of the annular oscillator, the second tuningterminal is connected with the frequency fine tuning loop, and the frequency rough tuning loop is connected with the annular oscillator. The phase-locked loop frequency synthesizer disclosed by the invention has the advantages that the frequency rough tuning loop selects a target sub frequency band with the center working frequency tending to target frequency from numerous sub frequency bands ofthe annular oscillator, thereby realizing frequency rough tuning; after the obtained target sub frequency band is subjected to rough tuning, a variable tuning voltage is generated and output by virtueof the frequency fine tuning loop, and the tuning varactor is driven to be continuously tuned in the target sub frequency band range; and voltage-frequency tuning gain of a voltage-controlled oscillator is reduced, thus noise sensitivity of the phase-locked loop frequency synthesizer on a control voltage is reduced.

Description

technical field [0001] The invention belongs to the technical field of phase-locked loops, and relates to a low-power-consumption phase-locked loop frequency synthesizer. Background technique [0002] PLL frequency synthesizers are widely used in integrated circuits to provide multi-phase clock signals for digital circuits, data converters, chip interfaces, etc. Such PLL frequency synthesizers are usually implemented based on ring oscillators. Because the phase noise performance of the ring oscillator is poor, it is a key factor restricting the noise performance of the ring oscillator phase-locked loop. In order to obtain better output phase noise performance, the phase-locked loop usually adopts a larger loop bandwidth to suppress the phase noise of the ring oscillator, so as to achieve the purpose of optimizing the output phase noise performance of the phase-locked loop. [0003] Traditional ring oscillators such as figure 1 As shown, the phase-locked loop usually uses ...

AI Technical Summary

Problems solved by technology

Such a large gain makes the PLL noise particularly sensitive and affects the noise performance of the PLL

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