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Three-dimensional semiconductor devices

A semiconductor and device technology, applied in the field of three-dimensional semiconductor devices

Active Publication Date: 2018-11-02
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there are significant fabrication hurdles in achieving low-cost, high-volume production of 3D semiconductor devices, especially in high-volume fabrication of 3D devices that maintain or exceed the operational reliability of their 2D counterparts.

Method used

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  • Three-dimensional semiconductor devices
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Embodiment Construction

[0023] The inventive concept will now be described more fully with reference to the accompanying drawings, in which examples of the inventive concept are shown.

[0024] figure 1 is a circuit diagram schematically illustrating a cell region of an example of a three-dimensional semiconductor memory device according to the present inventive concept.

[0025] refer to figure 1 , the cell array of the three-dimensional semiconductor memory device may include a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR disposed between the common source line CSL and the bit lines BL.

[0026] The common source line CSL may be a conductive pattern provided on the substrate or an impurity region formed in the substrate. The bit lines BL may be conductive patterns (eg, metal lines) spaced vertically from the substrate. The bit lines BL may be arranged two-dimensionally, and a plurality of cell strings CSTR may be connected in parallel to each bit line...

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Abstract

A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least aportion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.

Description

technical field [0001] The inventive concept relates to a semiconductor device, and in particular, to a three-dimensional semiconductor device in which memory cells are three-dimensionally arranged. Background technique [0002] Higher integration of semiconductor devices is required to meet consumer demand for electronic products that provide superior performance at low prices. In the case of semiconductor devices, since their integration is an important factor in determining the price of a product, increased integration is particularly desired. In the case of general two-dimensional or planar semiconductor memory devices, since their integration is mainly determined by the area occupied by a unit memory cell, the integration is greatly influenced by the level of fine patterning technology. However, the very expensive process equipment required to increase the fineness of the pattern sets a practical limit to improving the integration of two-dimensional or planar semicondu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/115H01L27/11551
CPCH10B41/20H10B43/20H01L29/7827H10B43/35H10B43/27H01L21/823475H10B41/27H01L21/02532H01L29/0649H01L29/7926H01L29/66833H01L21/31144H01L21/31111H01L29/66553H01L29/518H01L29/513H01L21/0262H01L21/02636H01L29/1037H01L29/40117H10B43/10
Inventor 崔至薰金成吉金智美金泓奭南泌旭安宰永
Owner SAMSUNG ELECTRONICS CO LTD