A high-speed signal optimization method and system for a reference clock line

Abstract

The present invention provides a high-speed signal optimization method and system for a reference clock line. The method includes: S1. Determine the wiring layer distribution of the clock line on the surface layer and the inner layer according to the chip layout and the wiring of the signal line, and establish a wiring model. ; S2. Obtain the stacking information of the simulated waveform based on the routing model, and evaluate the propagation speed of the signal on the surface layer and the inner layer; S3. Set the routing length of the surface layer and the inner layer according to the signal propagation speed combined with the equal length requirement and the delay requirement . The present invention determines the wiring layer distribution of the clock line, calculates the signal propagation speed of each wiring layer according to the stacked layer information of the simulated waveform, and finally sets the length of each wiring layer in combination with the requirements of equal length and time delay, so as to realize the clock The optimal design of the signal line not only satisfies the physical equal length, but also meets the delay requirement, reduces the design risk of the link, avoids unforeseen problems, improves the success rate of the system design, and enhances the signal quality.

Description

technical field [0001] The invention relates to the field of digital system design, in particular to a high-speed signal optimization method and system for a reference clock line. Background technique [0002] High-speed interconnect phenomena are often negligible in traditional digital system designs because their impact on system performance is minimal in traditional digital systems. However, with the continuous development of computer technology, high-speed interconnection is playing a leading role among many factors that determine system performance, which often leads to some unforeseen problems and greatly increases the complexity of system design. [0003] In the process of designing high-speed signal links in server systems, the equal-length design of clock signal lines is very important. For example, in motherboard design, Intel recommends that the length difference between the reference clock and the CPU and peripheral devices be controlled within 5 inches. Only in...

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Problems solved by technology

[0005] The purpose of the present invention is to provide a high-speed signal optimization method and system for a reference clock line, aiming to solve the problem of blindly pursuing the physical equal-length design of the signal line in the existing design and ignoring the more critical delay requirements, and to achieve reduction The design risk of small links can avoid unforeseen problems and improve the success rate of system design

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