The invention provides a high-speed
signal optimization method and
system for reference
clock lines. The method comprises the following steps: S1, determining routing layer distributions of
clock lines in a
surface layer and an inner layer according to
chip layout and
signal line wiring condition thereof, and building a
routing model; S2, obtaining lamination information of a
simulation waveform based on the
routing model, and evaluating propagation speeds of signals in the
surface layer and the inner layer; and S3, setting routing lengths in the
surface layer and the inner layer by combiningan equal length requirement and a time
delay requirement and according to the
signal propagation speeds. The method provided by the invention has the advantages that the routing layer distributions ofthe
clock lines are determined, the signal propagation speed of each routing layer is calculated according to the laminate information of the
simulation waveform, and finally the length of each routing layer is set by combining the equal length requirement and the time
delay requirement, so that
optimal design of a
clock signal line is realized, on the basis that physical equal length is met, thetime
delay requirement is also met, a
link design risk is reduced, formation of unforeseeable problems is avoided,
system design success rate is improved, and
signal quality is enhanced.