High-speed signal optimization method and system for reference clock lines

Abstract

The invention provides a high-speed signal optimization method and system for reference clock lines. The method comprises the following steps: S1, determining routing layer distributions of clock lines in a surface layer and an inner layer according to chip layout and signal line wiring condition thereof, and building a routing model; S2, obtaining lamination information of a simulation waveform based on the routing model, and evaluating propagation speeds of signals in the surface layer and the inner layer; and S3, setting routing lengths in the surface layer and the inner layer by combiningan equal length requirement and a time delay requirement and according to the signal propagation speeds. The method provided by the invention has the advantages that the routing layer distributions ofthe clock lines are determined, the signal propagation speed of each routing layer is calculated according to the laminate information of the simulation waveform, and finally the length of each routing layer is set by combining the equal length requirement and the time delay requirement, so that optimal design of a clock signal line is realized, on the basis that physical equal length is met, thetime delay requirement is also met, a link design risk is reduced, formation of unforeseeable problems is avoided, system design success rate is improved, and signal quality is enhanced.

Description

technical field [0001] The invention relates to the field of digital system design, in particular to a high-speed signal optimization method and system for a reference clock line. Background technique [0002] High-speed interconnect phenomena are often negligible in traditional digital system designs because their impact on system performance is minimal in traditional digital systems. However, with the continuous development of computer technology, high-speed interconnection is playing a leading role among many factors that determine system performance, which often leads to some unforeseen problems and greatly increases the complexity of system design. [0003] In the process of designing high-speed signal links in server systems, the equal-length design of clock signal lines is very important. For example, in motherboard design, Intel recommends that the length difference between the reference clock and the CPU and peripheral devices be controlled within 5 inches. Only in...

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Problems solved by technology

[0005] The purpose of the present invention is to provide a high-speed signal optimization method and system for a reference clock line, aiming to solve the problem of blindly pursuing the physical equal-length design of the signal line in the existing design and ignoring the more critical delay requirements, and to achieve reduction The design risk of small links can avoid unforeseen problems and improve the success rate of system design

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