The invention provides high-speed level conversion circuit applied to a mixed
voltage output buffer. The circuit comprises a level conversion circuit and a VDDIO judgment circuit, and corresponding correct bias signals are provided for an output stage of the output buffer to drive a PMOS
transistor in different
voltage modes. VDDIO is the working mode
voltage of the output buffer and can be VDD and 2 * VDD, DOUT is a pulse
signal needing to be transmitted, and the VDDIO judgment circuit provides a
control signal VG2 for the level conversion circuit according to the VDDIO voltage. In the VDD mode of the output buffer, VG2 is logic '0', PM3 and PM4 are closed, NM3 and NM4 are respectively conducted or closed according to the level state of DOUT, and 0-VDD pulse signals are output. In the 2 *VDD mode, VG2 is logic '1', PM3 and PM4 are switched on, NM3 and NM4 are switched off, and VDD-2 * VDD pulse signals are output.
Voltage generation paths of different working
modes of VDDIO are controlled through the
logic gate so as to improve the speed of level conversion, and therefore the transmission frequency of the output buffer is improved.