IP core for realizing Powerlink industrial real-time Ethernet communication

Abstract

The invention discloses an IP core for realizing Powerlink industrial real-time Ethernet communication. The IP core is designed as a Powerlink industrial real-time Ethernet communication IP core builtin a FPGA; the IP core comprises a core layer of a Powerlink protocol stack and a MAC layer; and the core layer comprises an interrupt generator two, a synchronous data buffer module, an asynchronousdata buffer module, a controller two, a network state machine two, a data link state machine, an event register and a soft interface. The IP core for realizing the Powerlink industrial real-time Ethernet communication disclosed by the invention can be encapsulated as a standard component of the Powerlink industrial real-time Ethernet communication protocol stack, which can be combined with the user layer according to various application requirements, so as to realize different design schemes of master / slave station devices for the Powerlink industrial real-time Ethernet communication; the IPcore can be in the same FPGA as the application layer to realize the design of the master / slave station devices for the Powerlink industrial real-time Ethernet communication; and the IP core and the application layer can also be in the FPGA and a microprocessor separately to realize the design of the master / slave station devices for the Powerlink industrial real-time Ethernet communication.

Description

technical field [0001] The invention relates to an IP core in the field of industrial field bus technology, in particular to an IP core for realizing Powerlink industrial real-time Ethernet communication. Background technique [0002] The combination of CPU+FPGA is often used in the open Powerlink resource package to realize the Powerlink master station or slave station. The openPowerlink resource package discloses a method of using open MAC (HUB) and open Powerlink Applicationstack to design and implement a Powerlink master station or slave station. figure 1 It is an existing open Powerlink model diagram, openPowerlink protocol stack=user layer+session abstraction layer+kernel layer+MAC layer. Except that the MAC layer is implemented by hardware description language programming and runs on FPGA, the other layers are all implemented by computer high-level language programming and run on the upper computer CPU. [0003] The user layer is responsible for control, the kernel ...

AI Technical Summary

Problems solved by technology

[0006] The open Powerlink resource package is an entry-level C language protocol stack for Powerlink industrial real-time Ethernet communication. If you use the open Powerlink resource package to design and implement Powerlink industrial real-time Ethernet communication and product design, it is impossible to implement the "Ethernet Powerlink The technical indicators stipulated in "Communication Profile Specification" (GB / T 27960-2016)

It has the following disadvantages: large signal transmission jitter, slow transmission rate, long cycle period, multiple chips are required at the same time, and the design is complicated, which causes problems such as slow response of Powerlink industrial real-time Ethernet communication, unstable transmission, and high communication cost.

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