Planarization simulation method and system for FinFET (Fin Field Effect Transistor) device shallow trench isolation

Abstract

The invention discloses a planarization simulation method for FinFET (Fin Field Effect Transistor) device shallow trench isolation. The method comprises the following steps that: carrying out mesh generation on a chip layout, and independently extracting layout characteristic parameters in a mesh; obtaining a chip deposition surface elevation model of which the oxide is deposited so as to providethe initial surface topography elevation of the chip, wherein the chip deposition surface elevation model and the layout characteristic parameters are related; obtaining the pattern density in the mesh after the oxide is deposited; according to the graph density and characteristic relevant length in the deposited mesh, obtaining graph effective density in the mesh; obtaining contact pressure distribution in the chip surface mesh; according to the graph effective density and the contact pressure distribution in the mesh, establishing the grinding removal rate model of the chip; and taking the initial surface topography elevation of the chip as an initial value, and according to a relationship between the topography elevation and the grinding removal rate equation of the chip, carrying out chip surface topography simulation. By use of the method, the requirements of the planarization simulation of the FinFET device shallow trench isolation can be met.

Description

technical field [0001] The invention relates to the field of integrated circuit design and manufacture, in particular to a planarization simulation method and system for shallow trench isolation of FinFET devices. Background technique [0002] With the continuous development of integrated circuit technology, the requirements for integration are getting higher and higher. After entering the 16nm process node, the non-planar fin field effect transistor (Fin Field Effect Transistor, FinFET) structure is generally adopted in the industry. [0003] In the manufacturing process of FinFET, shallow trench isolation is formed between fins (Fin). In the formation step of shallow trench isolation, it is necessary to perform CMP after depositing silicon nitride (SiN) and oxide (Oxide). (chemical mechanical planarization), in the planarization process, SiN depression is a common problem, which will affect the height and shape of the fin, and directly affect the performance of the device ...

AI Technical Summary

Problems solved by technology

[0005] The present invention provides a flattening simulation method and system for shallow trench isolation of FinFET devices, in order to solve the shortcomings existing in the existing FinFET CMP simulation

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