Successive verification type safe scanning chain device and method based on logic encryption

A technology of security scanning and scan chain, applied in the field of successive verification type security scan chain structure, can solve the problem of chip security, malicious attack of scan chain, etc., and achieve the effect of ensuring testability and security, and resisting attack methods.

Inactive Publication Date: 2018-11-27
TIANJIN UNIV
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

[0004] However, the scanning test technology may bring potential security problems to the chip while improving the testing efficiency of the chip.
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  • Successive verification type safe scanning chain device and method based on logic encryption
  • Successive verification type safe scanning chain device and method based on logic encryption
  • Successive verification type safe scanning chain device and method based on logic encryption

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Embodiment Construction

[0022]The present invention proposes a sequentially verified security scan chain structure based on logic encryption, uses logic encryption technology to encrypt the traditional scan chain to prevent malicious attackers from reading the internal information of the circuit, and uses logic camouflage technology to camouflage the security scan chain , to prevent reverse analysis of the security logic chain structure. The security scan chain structure adds an identification and verification structure. When entering the test work mode, a certain password needs to be entered to scan input and output. If the attacker does not know the preset password in advance, the security scan chain structure cannot be effectively used. On the basis of ensuring the observability and controllability of the chip, the security scanning structure greatly improves the security level of the scan chain, effectively preventing the risk of leakage of chip information in private areas such as communication a...

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Abstract

The invention belongs to the technical field of safety testability of integrated circuits. On the basis of ensuring the observability and controllability of a chip, an identity identification and verification structure is added, inner secret key information is successively verified, the safety grade of a scanning chain is improved and the risk of the leakage of inner information of the chip is greatly reduced. According to the invention, the device comprises a secret key locking module Key, a sequence enabling module FSM and the scanning chain. When the secrete key locking module Key monitorsthat the key enters the test mode, whether the secret keys input by an input end S1 are correct is successively verified. When correct secret key information is input, the scanning chain is used for scanning input and scanning output. The sequence enabling module FSM successively carries out secret key verification on a secret key locking module of each grade after the circuit enters the test module. The device and the method are mainly applied to designing and detection occasions of the integrated circuits.

Description

technical field [0001] The invention belongs to the field of safety testability design of integrated circuits, and in particular relates to a successive verification type safety scanning chain structure based on logic encryption. Background technique [0002] With the rapid development of semiconductor technology and computer-aided design, more and more functions are integrated into a monolithic integrated circuit, and the scale of the circuit is also increasing accordingly. However, in the process of chip design and manufacturing, there is no guarantee that there will be no defects in design and manufacturing. Testing is the most important means to ensure chip quality, and an indispensable part of chip design and manufacturing. In order to ensure the performance and yield of the chip, the chip is usually tested for functional vulnerabilities, design defects, and manufacturing faults (stuck faults, bridging faults, and delay faults, etc.) during the testing phase. With the...

Claims

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Application Information

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IPC IPC(8): G01R31/28G06F21/44
CPCG01R31/2851G06F21/44
Inventor 赵毅强刘燕江马浩诚宋凯悦
Owner TIANJIN UNIV
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