Successive verification type safe scanning chain device and method based on logic encryption

Abstract

The invention belongs to the technical field of safety testability of integrated circuits. On the basis of ensuring the observability and controllability of a chip, an identity identification and verification structure is added, inner secret key information is successively verified, the safety grade of a scanning chain is improved and the risk of the leakage of inner information of the chip is greatly reduced. According to the invention, the device comprises a secret key locking module Key, a sequence enabling module FSM and the scanning chain. When the secrete key locking module Key monitorsthat the key enters the test mode, whether the secret keys input by an input end S1 are correct is successively verified. When correct secret key information is input, the scanning chain is used for scanning input and scanning output. The sequence enabling module FSM successively carries out secret key verification on a secret key locking module of each grade after the circuit enters the test module. The device and the method are mainly applied to designing and detection occasions of the integrated circuits.

Description

technical field [0001] The invention belongs to the field of safety testability design of integrated circuits, and in particular relates to a successive verification type safety scanning chain structure based on logic encryption. Background technique [0002] With the rapid development of semiconductor technology and computer-aided design, more and more functions are integrated into a monolithic integrated circuit, and the scale of the circuit is also increasing accordingly. However, in the process of chip design and manufacturing, there is no guarantee that there will be no defects in design and manufacturing. Testing is the most important means to ensure chip quality, and an indispensable part of chip design and manufacturing. In order to ensure the performance and yield of the chip, the chip is usually tested for functional vulnerabilities, design defects, and manufacturing faults (stuck faults, bridging faults, and delay faults, etc.) during the testing phase. With the...

AI Technical Summary

Problems solved by technology

[0004] However, the scanning test technology may bring potential security problems to the chip while improving the testing efficiency of the chip.

For the high controllability and observability of the scan chain, the possibility that the scan chain may be used by malicious attackers for malicious attacks has increased significantly

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