Preventing Dynamic Obfuscation of Scan Chain Structures Using Scan Chains to Attack Integrated Circuit Chips

An integrated circuit and scan chain technology, applied in the field of intellectual property and security protection of integrated circuit chips, can solve problems such as being breached, and achieve the effects of low additional area and power consumption, small design and test procedures, and increased test time.

Active Publication Date: 2019-03-05
BEIHANG UNIV
View PDF6 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, with the continuous development of new technologies, these methods have the possibility of being broken

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Preventing Dynamic Obfuscation of Scan Chain Structures Using Scan Chains to Attack Integrated Circuit Chips
  • Preventing Dynamic Obfuscation of Scan Chain Structures Using Scan Chains to Attack Integrated Circuit Chips
  • Preventing Dynamic Obfuscation of Scan Chain Structures Using Scan Chains to Attack Integrated Circuit Chips

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0061] Apply the integrated circuit chip designed by the present invention to dynamically confuse the scan chain structure for testing:

[0062] The IC chip dynamic confusion scan chain structure proposed by the present invention has been inserted into several test circuits, such as the FGU (Floating Point and Graphic Unit, floating-point calculation and image processing module) module in the OpenSPARCT2 processor, the largest in ITC'99 In the circuit b19, a 128-bit AES encryption module, and the Leonprocessor, Leon3s and VGA-LCD modules in the Gaisler chip, all the test circuits set the function clock to 100MHz and the scan clock to 10MHz during synthesis, and the scan chain The maximum length is 64 (that is, λ=64). It should be pointed out that since the number of scanning units in the integrated circuit chip is not necessarily an integer multiple of 64, the synthesis tool will automatically balance the length of each scanning chain so that the maximum length is 64. And the ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a dynamic mixed scanning chain structure for protecting an integrated circuit chip from being attacked through a scanning chain, and the structure consists of a control unit (1A), a linear feedback displacement shift register (1B), a shielding chain (1C), and an exclusive-OR gate set (1D). The structure consists of all digital elements, is embedded into an integrated circuit, and can mix the scan chain structure in the integrated circuit chip, so the input excitation and output response obtained by a tester are obtained through mixing. An attacker is difficult to obtain the real test input / output and scanning chain structure, thereby achieving a purpose of protecting the integrated circuit chip. The structure can protect the integrated circuit chip from being affected by a non-destruction chip attack based on the scanning chain, and prevents the internal sensitive information of the chip from being leaked. Meanwhile, the needed additional area and power consumption are very small, the impact on the design of an original integrated circuit chip and a test flow is small, and the test time cannot be increased.

Description

technical field [0001] The present invention relates to a dynamic obfuscation scan chain structure for preventing the use of scan chains to attack integrated circuit chips, more precisely, it is a dynamic obfuscation scan chain suitable for preventing attackers from using scan links to attack integrated circuit chips in the supply chain The circuit structure belongs to the technical field of integrated circuit chip intellectual property and security protection. Background technique [0002] An integrated circuit (integrated circuit) is a tiny electronic device or component. It is a semiconductor manufacturing process such as oxidation, photolithography, diffusion, epitaxy, aluminum evaporation, etc., which integrates semiconductors, resistors, capacitors and other components required to form a circuit with certain functions and the connecting wires between them into a small piece of silicon. On-chip, and then welded electronic devices packaged in a tube; all the components ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/3167G01R31/3177G01R31/317
CPCG01R31/3167G01R31/31718G01R31/31719G01R31/3177
Inventor 王晓晓张东嵘苏东林陈爱新
Owner BEIHANG UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products