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Scanning circuit element and method for selecting scanning mode of scanning circuit element

A technology for scanning circuits and components, applied to logic circuits using basic logic circuit components, electronic circuit testing, logic circuits using specific components, etc., can solve problems such as wasting power

Inactive Publication Date: 2018-12-07
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Such DFT components are irrelevant to the normal (non-test mode) operation of the IC and waste power during normal operation of the IC due to switching and / or leakage currents

Method used

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  • Scanning circuit element and method for selecting scanning mode of scanning circuit element
  • Scanning circuit element and method for selecting scanning mode of scanning circuit element
  • Scanning circuit element and method for selecting scanning mode of scanning circuit element

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Embodiment Construction

[0017] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood by those skilled in the art that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the herein disclosed subject matter.

[0018] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment disclosed herein. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" or "according to an embodiment" (or other phrases of similar import) in various places throughout this specification may not all refer to the same embodiment. Furthermore, the particular features, st...

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PUM

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Abstract

The present invention provides a scanning circuit element and a method for selecting a scanning mode of a scanning circuit element. The scanning circuit element includes a data path and a scan-data path that are respectively selected in response to a first operational mode and a second operational mode. The scan-data path includes an input element having an input node, an output node, a first power node and a second power node. A signal path between the input node and the output node is part of the scan-data path. The first power node is coupled to a first voltage potential, and the second power node is coupled to a mode-control signal that is at substantially the first voltage potential in the first operational mode and that is at substantially a second voltage potential in the second operational mode. In the second operational mode, the scanning element exhibits no switching current and no leakage current.

Description

[0001] This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 511,318, filed May 25, 2017, and U.S. Patent Application No. 15 / 663,580, filed July 28, 2017, which are incorporated by reference in their entirety here. technical field [0002] The subject matter disclosed herein relates to scannable circuits. More specifically, the subject matter disclosed herein relates to a system and method for reducing power consumption and leakage current of scannable circuits. Background technique [0003] Scan chain testing is a Design for Test (DFT) technique that embeds hardware components into an integrated circuit (IC) design to detect manufacturing faults in the IC. The testability features of a DFT component may be configured as sequential elements (eg, flip-flops, latches, etc.) within a sequential logic path capable of operating in a scannable mode (ie, test mode). Such DFT components are not relevant to the normal (non-test mode) operatio...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/3185G01R31/28G01R31/50
CPCG01R31/2851G01R31/318536G01R31/318544G01R31/318575H03K19/0016H03K19/173G01R31/50
Inventor 马修·贝尔津什
Owner SAMSUNG ELECTRONICS CO LTD