Semiconductor structure and forming method thereof, forming method of fin-type field effect transistor

A semiconductor and isolation structure technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as easy bridging, reduce the probability of gaps, improve electrical performance and yield, and reduce bridging problems.

Active Publication Date: 2018-12-14
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the fin field effect transistor formed in the prior art is prone to bridging problems after the stress layer is introduced.

Method used

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  • Semiconductor structure and forming method thereof, forming method of fin-type field effect transistor
  • Semiconductor structure and forming method thereof, forming method of fin-type field effect transistor
  • Semiconductor structure and forming method thereof, forming method of fin-type field effect transistor

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Embodiment Construction

[0019] It can be seen from the background art that the fin field effect transistor introduced with the stress layer in the prior art is prone to bridging problems. Now combine the formation method of a semiconductor structure to analyze the cause of its bridging problem:

[0020] refer to Figure 1 to Figure 2 , shows a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0021] refer to figure 1 , providing a substrate 11 with discrete fins 12 on the substrate 11; forming an isolation structure 13 on the substrate 11 exposed by the fins 12; forming an isolation structure 13 on the fins 12 and the isolation structure 13 A dummy gate structure 14 across the fin 12 , the dummy gate structure 14 covers part of the top and part of the sidewall surface of the fin 12 ; sidewalls 15 are formed on the sidewall of the dummy gate structure 14 .

[0022] combined reference figure 2 , figure 2 yes figure 1 A schematic diagra...

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PUM

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Abstract

The invention provides a semiconductor structure and forming method thereof, forming method of fin-type field effect transistor. The forming method includes provide a substrate having discrete fins, an isolation structure between fins, and a dummy gate structure across that fin, wherein a top portion of the isolation structure is lower than the top portion of the fin; Forming a sidewall located atleast on a sidewall of the dummy gate structure; Forming a sacrificial layer on the isolation structure; After forming the sacrificial layer, a first groove is formed in the fins on both sides of thedummy gate structure. The sacrificial layer can play a role of protecting the isolation structure during the formation of the first groove, can effectively reduce the occurrence of the isolation structure loss phenomenon, thereby reducing the occurrence probability of bridging problems, and is conducive to improving the electrical performance and yield of the formed semiconductor structure.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof, and a forming method of a fin field effect transistor. Background technique [0002] With the gradual development of semiconductor process technology, the development trend of semiconductor process nodes following Moore's Law continues to decrease. In order to adapt to the reduction of process nodes, the channel length of MOSFET field effect transistors has to be continuously shortened. The shortening of the channel length has the advantages of increasing the die density of the chip and increasing the switching speed of the MOSFET field effect tube. [0003] However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel becomes worse, resulting in the phenomenon of subthreshold leakage, the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/78
CPCH01L29/66795H01L29/785
Inventor 李勇
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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