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Timing control circuit

A technology of timing control circuit and level, applied in the direction of logic circuit interface device, logic circuit connection/interface layout, electrical components, etc., can solve the problems of difficulty in implementation, a lot of time, labor cost, complicated design, etc., to reduce work The effect of avoiding the shortage of IO port resources and low hardware cost

Inactive Publication Date: 2018-12-14
SHENZHEN XINGUODU TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] like figure 1 , the existing timing control circuit schemes are all controlled by timing ICs, or using the CPU to control the power enable pins separately. Although these schemes have been widely used, such designs are costly and complex, and require more CPU pins Resources, more complex software execution algorithms, so a lot of time and labor costs are required to design circuits and write software, and these two solutions are difficult to achieve when the system IO port resources are limited and the PCB board space is limited.

Method used

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Examples

Experimental program
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Effect test

Embodiment 1

[0024] see figure 2 , a timing control circuit, including a discharge unit, a power-on unit, a first level unit, a second level unit and a third level unit, one end of the discharge unit is connected to the reset port, and the other end is connected to the output of the power-on unit end, the output end of the power-on unit is also connected to the first level unit, the second level unit and the third level unit cascaded, and the output end of the third level unit is connected to the ground through a resistance to ground .

[0025] The discharge unit is used to slow down the power-on speed of VCC-1, VCC-2 and VCC-3. The discharge unit includes a first resistor R1 and a first capacitor C1, the input terminal of the discharge unit is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to one end of the first capacitor C1 , the other end of the first capacitor C1 is connected to the output end of the discharge unit.

[0026] ...

Embodiment 2

[0032] On the basis of Embodiment 1, the first capacitor C1 is made of NPO material.

[0033] In this embodiment, the NPO capacitor is one of the capacitors with the most stable capacitance and dielectric loss. When the temperature is from -55°C to +125°C, the capacity change is 0±30ppm / °C, and the change of capacitance with frequency is less than ±0.3ΔC. The drift or hysteresis of NPO capacitors is less than ±0.05%, which is negligible relative to film capacitors greater than ±2%. Its typical variation of capacity relative to service life is less than ±0.1%.

[0034] The use of NPO capacitors is beneficial to the reliability of the timing control circuit.

Embodiment 3

[0036] On the basis of Embodiment 2, the resistance value of the first resistor R1 is 0Ω, the capacitance value of the first capacitor C1 is 4.7UF; the resistance value of the second resistor R2 is 5.1KΩ, and the power of the second resistor R2 is 1 / 20W; the type of diode D1 is 1N4148WT; the resistance of the third resistor R3 is 150KΩ, and the power of the third resistor R3 is 1 / 20W; the resistance of the fourth resistor R4 is 27KΩ, and the fourth resistor The power of R4 is 1 / 20W; the resistance value of the fifth resistor R5 is 10KΩ, and the power of the fifth resistor R5 is 1 / 20W; the resistance value of the ground resistance R6 is 120KΩ, and the power of the ground resistance R6 is 1 / 20W.

[0037] In this embodiment, selecting resistors, capacitors, and diodes with appropriate specifications can increase the reliability of the circuit and achieve precise timing control.

[0038] see image 3 , the moment the circuit is powered on, the reset signal RESET remains low for ...

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Abstract

A timing control circuit include a discharge imot, power-on unit, first level unit, and second level unit and third level unit, wherein one end of the discharge unit is connected with a reset port and the other end is connected with an output end of the power-on unit, the output end of the power-on unit is also connected with the first level unit, the second level unit and the third level unit arranged in cascade, and the output end of the third level unit is connected with ground through a resistance to ground. The invention has the advantages that: a sequential control circuit of discrete component design without CPU IO control and low hardware cost is provided. This scheme does not cause poor sequential control, and can avoid the shortage of IO port resources in hardware design, whichgreatly reduces the design cost of the whole machine and the workload of software designers.

Description

technical field [0001] The invention relates to the technical field of power supply control, in particular to a timing control circuit. Background technique [0002] POS machine is a multi-functional terminal, which can be installed in special merchants and acceptance outlets of credit cards to form a network with computers to realize automatic transfer of electronic funds. It has the functions of supporting consumption, pre-authorization, balance inquiry and transfer, etc. It is safe, fast and reliable to use, and is widely used in supermarkets, chain stores, hypermarkets, restaurants and other places. As a mobile electronic terminal, it will involve the operation of switching on and off, so there must be power on and off, and the power on and off sequence of the power supply is very important for electronic equipment, especially for POS machines that involve financial security, because in addition to functions In addition to being affected, it will also involve the trigge...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K17/22H03K19/0175
CPCH03K17/22H03K19/017509
Inventor 王奔尹奇红杨星倪丽娜
Owner SHENZHEN XINGUODU TECH