SRAM memory cell

Abstract

The invention discloses an SRAM memory cell, which is composed of two groups of P-type cross-coupling latch structures, two groups of N-type cross-coupling latch structures and four N-type transfer tubes. The invention not only can realize the function of resisting soft error, but also can work under the near threshold voltage.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to an SRAM (Static Random Access Memory) storage unit. Background technique [0002] The continuous advancement of integrated circuit technology nodes has brought many challenges to the reliability of the chip, one of which is the soft error caused by the single event upset (SEU) caused by the single event effect. [0003] Soft errors can occur in different electronic devices such as automotive electronics, medical devices, etc. [0004] In recent years, due to the continuous advancement of process nodes, the distance between devices has become closer and smaller, and the size of devices has become smaller and smaller, which makes single event upset an important source of soft errors. [0005] In addition, low-voltage operation is more and more widely used in wearable devices, implanted medical devices, smart grids, wireless sensor networks, etc. Most of the existin...

AI Technical Summary

Problems solved by technology

[0005] In addition, low-voltage operation is more and more widely used in wearable devices, implanted medical devices, smart grids, wireless sensor networks, etc. Most of the existing SRAM memory cells that are resistant to soft errors cannot read and write correctly under low voltage

Although the traditional 6-tube SRAM memory unit can read and write correctly under low voltage, it does not have the function of anti-soft error

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