SRAM memory cell

A storage unit and latch technology, used in information storage, static memory, read-only memory, etc., can solve the problems of lack of anti-softening, SRAM storage cells cannot be read and written, errors, etc., to achieve low read data time, Effects of high read static noise tolerance

Inactive Publication Date: 2018-12-28
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
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  • Claims
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Problems solved by technology

[0005] In addition, low-voltage operation is more and more widely used in wearable devices, implanted medical devices, smart grids, wireless sensor networks, etc. Most of the existing SRAM memory cells that are resistant to soft errors cannot read and write correctly under low voltage
Although the traditional 6-tube SRAM memory unit can read and write correctly under low voltage, it does not have the function of anti-soft error

Method used

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Embodiment Construction

[0022] combine figure 1 As shown, in the following embodiments, the SRAM storage unit is composed of two sets of P-type cross-coupled latch structures, two sets of N-type cross-coupled latch structures, and four N-type transmission transistors, forming a possible The 12-transistor soft-error-resistant SRAM memory cell that works near the threshold voltage has the function of fast reading and writing.

[0023] The source of the PMOS transistor PM1 and the source of the PMOS transistor PM2 are connected to the power supply voltage terminal VDD, the gate of the PMOS transistor PM1 is connected to the drain of the PMOS transistor PM2, and the connected node is marked as Q, and the gate of the PMOS transistor PM2 The pole is connected to the drain of the PMOS transistor PM1, and the node connected thereto is denoted as A, forming a first group of P-type cross-coupled latch structures.

[0024] The source of the PMOS transistor PM3 and the source of the PMOS transistor PM4 are conn...

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Abstract

The invention discloses an SRAM memory cell, which is composed of two groups of P-type cross-coupling latch structures, two groups of N-type cross-coupling latch structures and four N-type transfer tubes. The invention not only can realize the function of resisting soft error, but also can work under the near threshold voltage.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to an SRAM (Static Random Access Memory) storage unit. Background technique [0002] The continuous advancement of integrated circuit technology nodes has brought many challenges to the reliability of the chip, one of which is the soft error caused by the single event upset (SEU) caused by the single event effect. [0003] Soft errors can occur in different electronic devices such as automotive electronics, medical devices, etc. [0004] In recent years, due to the continuous advancement of process nodes, the distance between devices has become closer and smaller, and the size of devices has become smaller and smaller, which makes single event upset an important source of soft errors. [0005] In addition, low-voltage operation is more and more widely used in wearable devices, implanted medical devices, smart grids, wireless sensor networks, etc. Most of the existin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/04G11C16/10G11C16/26
CPCG11C16/0483G11C16/10G11C16/26
Inventor 蒋建伟
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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