A reliability evaluation method for nano-integrated circuits under the influence of multiple transient faults

Abstract

The invention provides a nano integrated circuit reliability evaluation method under the influence of multiple transient faults, comprising the following steps: 1, establishing a circuit reliability calculation formula of the nano integrated circuit to be evaluated; 2, determining the parameter value of the zero-fault direct current component in the reliability calculation formula; 3, performing single-fault simulation on a nano integrated circuit to be evaluate to evaluate a first-order principal component in a circuit reliability calculation formula; 4, carrying out dual-fault simulation onthat nano integrated circuit to be evaluated; 5, carrying out probability statistical analysis on the data obtained from the double-fault simulation to evaluate the second-order components in the circuit reliability calculation formula.

Description

technical field [0001] The present invention relates to the field of integrated circuit reliability evaluation; more specifically, the present invention relates to a method for evaluating the reliability of nanometer integrated circuits under the influence of multiple transient faults. Background technique [0002] Integrated circuit technology is an important part of modern electronic information technology. In the current complex and ever-changing international environment, the development of a highly reliable and self-controllable chip industry is particularly important. With the gradual maturity of nanotechnology, the scale of the circuit continues to increase, the feature size of the device continues to shrink, and the performance of the chip is improved, but at the same time, the transient faults caused by various energy particles in the space radiation environment are also It brings serious challenges to the reliability of the circuit. [0003] Transient fault is a ...

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Problems solved by technology

[0006] However, although system-level reliability analysis can provide designers with quantitative results of reliability in the early stage of integrated circuit design, guide fault-tolerant design as early as possible, and help balance reliability requirements and fault-tolerance overhead; The specific logic implementation of the circuit is not accurate enough for the reliability evaluation results of the circuit as a whole

[0007] In addition, the low-level circuit-level analysis method takes into account the underlying implementation of the circuit and environmental factors, and can simulate the behavior characteristics of the fault more realistically, and the evaluation results are relatively accurate; It is at least 3-4 orders of magnitude higher than the middle and high-level evaluation methods, and it is difficult to apply to fault analysis and reliability evaluation of large-scale circuits

[0008] In addition, logic-level evaluation methods can better balance efficiency and accuracy, but most existing methods only consider the impact of single transient faults on the circuit

The considerations become more complex when multiple faults are involved

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