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[0011] However, in the semiconductor device having the above structure, the parasitic capacitance formed between the JG electrode and the drain electrode, more specifically, the parasitic capacitance formed by the polarization junction (Polarization Junction) is relatively large.
Therefore, it takes time to charge the parasitic capacitance when the switching device is turned off, and the turn-off of the JFET formed on the JG electrode side is slowed down, which is not conducive to high-speed switching.
[0012] In addition, in the case of configuring a switching device with a 4-terminal structure, it is conceivable to electrically connect the JG electrode and the source electrode with a bonding wire so that they have the same potential. However, if such a connection form is made, the JG electrode and the source electrode will The impedance between the electrodes becomes larger, which is not conducive to high-speed switching
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no. 1 Embodiment approach
[0042] refer to Figure 1 to Figure 8 The semiconductor device of the first embodiment will be described. in addition, figure 1 It is a cross-sectional view showing an element of one unit included in the semiconductor device of the present embodiment, and the semiconductor device is configured by including a plurality of the units.
[0043] Such as figure 1 As shown, the semiconductor device of the present embodiment has a structure including a four-terminal HEMT as a horizontal switching device.
[0044] The switching device of the present embodiment uses a structure in which an undoped GaN (hereinafter referred to as u-GaN) layer 2 is formed on the surface of a substrate 1 as a compound semiconductor substrate. An undoped AlGaN (hereinafter referred to as u-AlGaN) layer 3 is formed on the surface of the u-GaN layer 2 , and the u-GaN layer 2 and the u-AlGaN layer 3 form a heterostructure structure. The switching device uses these u-GaN layer 2 and u-AlGaN layer 3 as chann...
no. 2 Embodiment approach
[0089] A second embodiment will be described. In this embodiment, the gate structure portion is changed from that of the first embodiment. Others are the same as those of the first embodiment, so only the parts different from the first embodiment will be described.
[0090] Such as Figure 9 As shown, in this embodiment, in order to realize the low resistance of the MOS gate electrode 7 in the gate structure portion, the MOS gate electrode 7 is made into a T-shape. That is, a T gate structure is formed in which the upper portion of the MOS gate electrode 7 is wider than the lower portion in the direction in which current flows between the source and the drain. In other words, the MOS gate electrode 7 is extended outside the notch 5 so as to protrude further toward the source electrode 8 and drain electrode 9 than the notch 5 . In addition, the metal layer 7a formed on the surface portion of the MOS gate electrode 7 protrudes further toward the source electrode 8 side and the...
no. 3 Embodiment approach
[0093] A third embodiment will be described. In this embodiment, the layout of the pads is changed from that of the first embodiment, and the rest is the same as that of the first embodiment, so only the parts different from the first embodiment will be described.
[0094] Such as Figure 10 As shown, in this embodiment, the source pad 15 and the drain pad 16 are arranged in the active region 14 . The source pad 15 is configured by enlarging the area of the electrode layer 13 connecting the source electrode 8 and the JG electrode 11 . In the case of this embodiment, the area can be made larger by connecting the electrode layers 13 between adjacent cells.
[0095] In this way, by arranging the source pad 15 in the active region 14, the wiring length from the source electrode 8 and the JG electrode 11 to the source pad 15 can be shortened, and the wiring resistance can be reduced. Impedance decreases. As a result, a switching device further realizing high-speed switching i...
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Abstract
A JG electrode (11) and a source electrode (8) are directly coupled together via an electrode layer (13). This allows for a reduction in the resistance value of a parasitic impedance (50) and a reduction in the impedance between the JG electrode (11) and the source electrode (8). Further, a u-GaN layer (4) and a p-GaN layer (10) are disposed apart from a drain electrode (9). This allows for a reduction in the area of overlap between a p-GaN layer (4) and a 2-DEG, making it possible to reduce a feedback capacitance (C1). Thus the impedance between the JG electrode (11) and the source electrode(8) and the feedback capacitance (C1) can be reduced to increase a current (Ijg) flowing when the feedback capacitance (C1) is charged. Therefore, the feedback capacitance (C1) can be rapidly charged,making it possible to rapidly turn off a JFET part (40) and thereby further increase the turn-off speed of a switching device.
Description
[0001] Cross-references to related applications [0002] This application claims priority based on Japanese Patent Application No. 2016-103352 filed on May 24, 2016 and Japanese Patent Application No. 2016-237723 filed on December 7, 2016, and the descriptions thereof are incorporated herein by reference. technical field [0003] The present invention relates to a substrate having a heterostructure structure formed of a first GaN-based semiconductor layer and a second GaN-based semiconductor layer by laminating galliumnitride (hereinafter referred to as GaN), aluminum gallium nitride (hereinafter referred to as AlGaN), or the like on a substrate. semiconductor device. Background technique [0004] Conventionally, in Non-Patent Document 1, a HEMT (High electron mobility transistor) with a four-terminal structure has been proposed as a horizontal switching device having a heterostructure structure. [0005] In this switching device, a heterostructure structure is formed by l...
Claims
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