A Differential Leakage Compensation Charge Pump Circuit

Abstract

The present invention relates to a leakage compensation charge pump circuit with a differential structure, wherein the circuit includes an UP control circuit receiving an UP electrical signal, a UPB control circuit receiving an inverted UP electrical signal, a DN control circuit receiving a DN electrical signal, and The DNB control circuit that receives the inverted DN electrical signal; when the UP electrical signal input by the frequency detector and phase detector is at a low level, the UP control circuit is turned off, and the UPB control circuit is turned on. At this time, the current input to the NMOS tube is controlled by The UPB control circuit is provided to avoid the current leakage of the UP control circuit; it also includes: a differential amplifier circuit and a follower amplifier circuit, a differential amplifier circuit, which is used to differentially amplify or reduce the input DN electrical signal and DNB electrical signal into a DNX electrical signal and The DPX electrical signal is input to the DN control circuit and the DNB control circuit to reduce the noise of the DN electrical signal and the DNB electrical signal; the follower amplifier circuit is used to make the DNB control circuit when the UP electrical signal and the DN electrical signal are both low. The output voltage Vcon remains unchanged.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a leakage compensation charge pump circuit with a differential structure. Background technique [0002] When the manufacturing process enters the era of nanometer design, if the high-resistance nodes in the circuit have a large number of current leakage paths during operation, this will lead to a decrease in chip performance, such as in the application of a phase-locked loop (PLL) clock system charge pump circuit. There are various leakage compensation schemes to solve this problem. The first solution is to use a relatively large charge pump current (like 100uA or higher) to reduce leakage current effects, which may be fine if the PLL loop design happens to use a larger charge pump current Yes, but not always. [0003] The second solution is based on a diode connected path such as figure 1 Shown is a PLL circuit based on a charge pump. The input current Ichp is output to...

AI Technical Summary

Problems solved by technology

However, in practical applications, the switches S1 and S2 are two MOS tubes, and the UP and DN output by the frequency and phase detector are both low level, and the two MOS tubes actually allow a small part of the current to flow into the ground, so that As a result, the current input to the loop filter will gradually decrease, that is, the voltage Vcon will gradually decrease, such as figure 2 As shown by the dotted line in the IV section of the middle, resulting in leakage problems in the PLL circuit

Images