Test structure and test method
A technology of testing structure and testing method, which is applied in semiconductor/solid-state device testing/measurement, electrical components, circuits, etc. It can solve the problems of failure to detect whether the dielectric layer between metal layers is broken and the electrical failure of semiconductor devices, etc., to achieve The effect of easy layout, high controllability and easy operation
Active Publication Date: 2020-08-28
SEMICON MFG INT TIANJIN +1
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Problems solved by technology
[0003] With the increasing integration of semiconductor devices and the diversification of device packaging methods, the frequency of cracking of the dielectric layer between metal layers is also increasing. sexual failure
However, there is currently no test structure and test method that can detect whether the inter-metal dielectric layer is broken
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[0025] Generally, the metal interconnection layer structure in a semiconductor device includes more than two metal layers, an inter-metal dielectric layer, and a metal via. To the Nth metal layer, where N is an integer greater than or equal to 2, the substrate may include but not limited to a semiconductor substrate and a corresponding semiconductor structure (such as a gate, a source or a drain, etc.) located on the semiconductor substrate ); the inter-metal dielectric layer is located between two adjacent metal layers; the metal via is formed in the inter-metal dielectric layer for connecting two adjacent metal layers. The applicant found through practice that when the morphology of the above-mentioned semiconductor device is inspected by a scanning electron microscope (Scanning Electron Microscope, SEM) or a transmission electron microscope (Transmission Electron Microscope, TEM), it will be observed that there are cracks in the above-mentioned inter-metal dielectric layer ...
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The invention discloses a test structure and a test method. The test structure includes an N-layer metal layer, wherein N is an integer greater than or equal to 2, and the N-layer metal layer includesat least one first-type metal layer having a first metal line and at least one second type of metal layer having two or more second metal wires arranged at intervals, an inter-metal dielectric layerbetween two adjacent metal layers and between two adjacent second metal lines of the same layer; a metal through hole for connecting two adjacent metal layers; and test pads located in the same layeras the first type of metal layer under the second type of metal layer, wherein the test pads are located at both ends of the first metal line and electrically connected with the first metal line. Thetest method can effectively determine whether the inter-metal dielectric material is broken by monitoring the electrical parameters of the first metal layer connected to the test pads. The test structure is simple and the layout is easy; the test method is simple in operation and high in controllability.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a test structure and a test method. Background technique [0002] At present, after the device is prepared in the semiconductor front-end process, the metal interconnection layer structure is prepared in the semiconductor back-end process. The metal interconnection layer structure includes a multi-layer metal layer and a metal layer between two adjacent metal layers. The dielectric layer (Inter Metal Dielectric, IMD) and the metal vias located in the inter-metal dielectric layer, the metal vias are used to connect two adjacent metal layers, and the inter-metal dielectric layer is used to isolate two adjacent metal layers layer and adjacent metal vias, the inter-metal dielectric layer provides good insulation. [0003] With the increasing integration of semiconductor devices and the diversification of device packaging methods, the frequency of cracking of the dielectric...
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IPC IPC(8): H01L21/66
CPCH01L22/14H01L22/32
Inventor 陈福刚唐丽贤
Owner SEMICON MFG INT TIANJIN