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Semiconductor device and method of forming the same

A semiconductor and device technology, applied in the field of semiconductor devices and their formation, can solve problems such as performance to be improved, and achieve the effects of reducing etching loss, avoiding leakage, and small change in morphology

Active Publication Date: 2021-07-13
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the performance of semiconductor devices composed of MOS transistors in the prior art still needs to be improved

Method used

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  • Semiconductor device and method of forming the same
  • Semiconductor device and method of forming the same

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Experimental program
Comparison scheme
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Embodiment Construction

[0031] As mentioned in the background, semiconductor devices formed in the prior art have poor performance.

[0032] Figure 1 to Figure 2 It is a structural schematic diagram of a self-aligned etching process of a semiconductor device.

[0033] refer to figure 1 , provide a substrate 100, the substrate 100 includes a first region M and a second region N adjacent to the first region M; a gate structure and a dielectric layer 120 covering the gate structure are formed on the first region M of the substrate 100, the gate structure It includes a gate structure body 110 and a protective layer 112 located on the sidewall and top surface of the gate structure body 110 , and the dielectric layer 120 is also located on the second region N of the substrate 100 .

[0034] refer to figure 2 , forming a mask layer (not shown) on the dielectric layer 120 in the second region N; using the mask layer as a mask to etch and remove the dielectric layer 120 in the first region M, and forming ...

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Abstract

A semiconductor device and a method for forming the same, the method comprising: forming a first gate structure body on a first region of a substrate, a first initial protection layer located on the sidewall and top surface of the first gate structure body, and covering the first initial The first dielectric layer of the protective layer; etching and removing part of the first dielectric layer in the first region, so that the first dielectric layer in the first region forms a second dielectric layer, and exposes the first initial protective layer on the top of the first gate structure body and part of the first initial protection layer on the sidewall of the first gate structure body; performing at least one intermediate treatment process until the second dielectric layer is removed, and the first initial protection layer is formed on the sidewall and top of the first gate structure body For the first protection layer on the surface, the intermediate treatment process includes: after planarizing part of the first initial protection layer on the top of the first gate structure body, etching back part of the second dielectric layer in the first region. The method improves semiconductor device performance.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof. Background technique [0002] MOS (Metal-Oxide-Semiconductor) transistors are one of the most important components in modern integrated circuits. The basic structure of the MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, and the gate structure includes: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; The source and drain doped regions in the semiconductor substrate on both sides of the pole structure. [0003] The working principle of the MOS transistor is: a voltage is applied to the gate structure, and a switching signal is generated by adjusting the current in the channel at the bottom of the gate structure. [0004] However, the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/78
CPCH01L29/66795H01L29/785
Inventor 张城龙纪世良张海洋
Owner SEMICON MFG INT (SHANGHAI) CORP