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Semiconductor structures and methods of forming them

A semiconductor and gate layer technology, applied in the field of semiconductor structure and its formation, can solve the problem of high contact resistance of contact plugs, and achieve the effect of low contact resistance and reduced contact resistance

Active Publication Date: 2021-08-06
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, when the metal silicide is formed, the contact resistance between the metal gate and the contact plug above the metal gate is likely to be relatively large.

Method used

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  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0029] As described in the background, when the metal silicide layer is formed, it is easy to cause the contact resistance of the contact plug upper upper contact plug up to the metal gate.

[0030] Figure 1 to 2 It is a schematic structural diagram of a method of forming a semiconductor structure.

[0031] Please refer to figure 1 Provide a substrate 100 having a dummy gate layer (not shown), and the substrate 100 on both sides of the pseudo gate layer has a source leak-doped region 101; in the substrate 100 and The first dielectric layer 102 is formed on the source leak doping region 101, and the sidewall of the dummy gate layer; the dummy gate layer is removed, and the cockroacoustic opening is formed in the first dielectric layer 102 (not marked in the figure). The gate layer 103 is formed in the fake gate opening; a second dielectric layer 104 is formed on the first dielectric layer 102 and the gate layer 103; the first dielectric layer 102 on the source drain region 101 is ...

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Abstract

A semiconductor structure and a method for forming the same, wherein the method includes: providing a substrate with a gate layer on the substrate, impurity ions in the gate layer, source and drain doped regions in the substrate on both sides of the gate layer, the substrate, source and drain There is a dielectric layer on the doped region and the gate layer; remove part of the dielectric layer on the source-drain doped region until the source-drain doped region is exposed, and form a source-drain contact hole in the dielectric layer; remove part of the gate layer Dielectric layer, until the gate layer is exposed, a gate contact hole is formed in the dielectric layer; a barrier layer is formed at the bottom of the gate contact hole; a metal layer is formed on the barrier layer and the bottom of the source-drain contact hole; annealing is performed to make the The metal layer reacts with the source and drain doping region material at the bottom of the source and drain contact holes to form a metal silicide layer at the bottom of the source and drain contact holes. The contact resistance of the device formed by the method is small.

Description

Technical field [0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method of forming thereof. Background technique [0002] With the continuous development of semiconductor technology, the size of the semiconductor device is constantly decreasing. As the size of the semiconductor device is reduced, the contact resistance of the MOS transistor is increasingly affected by the performance of MOS transistors and the entire semiconductor chip. In order to improve the performance of the semiconductor chip, it is necessary to reduce the contact resistance of the MOS transistor. In the contact resistance of the MOS transistor, due to the source, the area of ​​the drain is small, the contact resistance between the conductive plug is large, and the performance of the MOS transistor is large, so that the operating speed of the semiconductor device is greatly reduced. [0003] The formation process of the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238H01L27/092
CPCH01L21/823814H01L21/823828H01L27/092
Inventor 刘继全
Owner SEMICON MFG INT (SHANGHAI) CORP