Delay circuit

Abstract

The invention provides a delay circuit. The delay circuit comprises a current source circuit, a voltage adjusting circuit and a main delay circuit, and the main delay circuit comprises k sub-delay circuits mutually connected in series, wherein k is a natural number; each sub-delay circuit comprises a first-level CMOS inverter and a second-level CMOS inverter mutually connected in series; and a substrate and a source electrode of a PMOS transistor of the first-level CMOS inverter and a substrate and a source electrode of a PMOS transistor of the second-level CMOS inverter are mutually connectedto a first circuit connection point, and the voltage and the temperature of the first circuit connection point are in linear negative correlation. According to the delay circuit, the delay time has asmall temperature drift, a power supply voltage is replaced by the voltage adjusting circuit to supply power to the delay circuit, a current source provides a current in positive correlation with thetemperature, the voltage adjusting circuit enables a bias voltage to be in a relatively stable level, and the influence of fluctuation of a power supply on the delay time is small.

Description

technical field [0001] The invention belongs to the field of electronic circuits and semiconductors, in particular to a delay circuit. Background technique [0002] Such as figure 1 As shown, the existing delay circuit composed of CMOS inverters generally consists of a first-stage CMOS inverter 11 and a second-stage CMOS inverter 12 . Both the first-stage CMOS inverter 11 and the second-stage CMOS inverter are composed of PMOS transistors and NMOS transistors. In each stage of CMOS inverters, the gate of the PMOS transistor is connected to the gate of the NMOS transistor and is connected to the input end of the CMOS inverter of the stage; the drain of the PMOS transistor is connected to the drain of the NMOS transistor. connected to and connected to the output terminal of the CMOS inverter of this stage; the substrate and source of the NMOS transistor NM1 are connected to each other and grounded. The substrates and sources of the PMOS transistors at all levels are connect...

AI Technical Summary

Problems solved by technology

[0007] The problem to be solved by the present invention is to provide a delay circuit for the change of the delay time caused by the fluctuation of the power supply voltage in the existing delay circuit

Images