Manufacturing method of nitride high electron mobility transistor with multi-gate structure
A technology with high electron mobility and manufacturing method, applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve the problems of affecting device loss, the spacing can not be too small, etc., to achieve good protection, improve performance, small gate Effect of electrode spacing
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Embodiment 1
[0050] After the source electrode 44 and the drain electrode 45 are completed, as Figure 6 A dielectric layer 46 is deposited as shown, and the dielectric layer 46 covers the source electrode 44, the drain electrode 45 and the AlGaN barrier layer 43 at the same time. The materials that can be used for the dielectric layer 46 include silicon nitride (SiN) and silicon oxide (SiO 2 ), the deposition method of the dielectric layer 46 includes sputtering, electron beam evaporation, plasma enhanced chemical vapor deposition (PECVD), the preferred dielectric material and deposition method are SiN and PECVD, and the preferred thickness is 100-200nm.
[0051] Such as Figure 7 As shown, on the dielectric layer 46 between the source electrode 44 and the drain electrode 45, form windows 47 and 48 called gate feet, and the formation of gate feet windows 47 and 48 generally needs to be coated with a photoresist layer, exposed, Steps such as developing form a window in the photoresist la...
Embodiment 2
[0058] Such as Figure 5 After the completion of source electrode 44 and drain electrode 45 as shown, as Figure 13 As shown, the AA dielectric layer 61 and the B dielectric layer 62 are sequentially deposited on the source electrode 44, the drain electrode 45 and the AlGaN barrier layer 43, and the material that can be used for the A dielectric layer 61 includes a single layer of SiO 2 or by SiN and SiO 2 Composite dielectric layer composed of SiO 2 When, its thickness is preferably 10-20nm; when it is SiN and SiO 2 When forming a composite dielectric layer, the layer in contact with the AlGaN barrier layer is SiN, the preferred thickness is 5-10nm, and the SiO on it 2 The thickness is preferably 10-20 nm. The B dielectric layer 62 is SiN, and its preferred thickness is 100-200 nm. The methods for depositing the A dielectric layer 61 and the B dielectric layer 62 include sputtering, electron beam evaporation, plasma enhanced chemical vapor deposition (PECVD), preferably ...
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