A read/write circuit of a parallel interface and a data read/write method

Abstract

The invention discloses a parallel interface read-write circuit and a data read-write method, which utilize an input processing unit, an address latch group connected with the input processing unit, adata flip-flop group and a BUS HOLD unit. The output of the address latch group is connected with an SEL unit, The output of the SEL unit is connected to the clock input of the data flip-flop group.As a result of the designed input processing unit, At that port, address signal A0 to An are chip-to-chip select signals CEn, Write signal WRn, the minimum value of the settling time of the read signal rdn may be 0, As long as that retention time meet the latch requirements, it can reduce the requirement of clock signal, As that asynchronous parallel interface adopt by the invention refers to thedifference between the external read / write clock and the internal clock of the circuit, or no external clock signal, this type of circuit requires low clock quality, especially when the external clockis not needed, the read and write data of the parallel interface is not limited by the clock signal, the design is flexible and simple, and the difficulty of the read and write design of the parallelinterface can be alleviated.

Description

technical field [0001] The invention belongs to the field of circuit design and relates to a parallel interface read-write circuit. Background technique [0002] In circuit design, circuit parallel interfaces generally include two types: synchronous and asynchronous, and are widely used in data exchange and communication. Synchronous parallel interface generally refers to the synchronization between the external read and write clock of the interface and the read and write signals of the circuit. This type of circuit has high requirements on the quality of the clock signal and strict requirements on the read and write timing. In the prior art, synchronous circuit design has the advantages of controllable design timing constraints and simple physical implementation. However, the design requires high clock signal quality and read / write timing, especially in high-speed parallel interface design, the signal quality is easily affected by system interference or design factors; Su...

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Problems solved by technology

However, the design requires high clock signal quality and read / write timing, especially in high-speed parallel interface design, the signal quality is easily affected by system interference or design factors; Sufficient design margin is left in the design to avoid the influence of process realization deviation

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