Radio frequency resistance model in an SOI process

Abstract

The invention discloses a radio frequency resistance model suitable for an SOI process, which comprises a resistance network used for representing a radio frequency resistance value through a plurality of resistors; the distributed capacitance network is used for simulating distributed capacitance of the radio frequency resistor through a plurality of capacitors; and the substrate equivalent network comprises a plurality of substrate equivalent network units formed by connecting resistors and capacitors in parallel, each equivalent network unit is connected with one capacitor of the distributed capacitor network and is used for simulating the resistance and the capacitance of the radio frequency resistor to the substrate, and the radio frequency resistance model which is good in impedanceperformance and is well matched with electromagnetic simulation is realized.

Description

technical field [0001] The invention relates to the technical field of simulation model design, in particular to a radio frequency resistance model in an SOI (Silicon-On-Insulator, ie, silicon on an insulating substrate) process. Background technique [0002] figure 1 It is a schematic diagram of a simulation model of a radio frequency resistance commonly used in a radio frequency circuit of the prior art, which includes a resistance network 10, a distributed capacitance network 20 and a substrate equivalent network 30, wherein the resistance network 10 is composed of 5 equal resistance resistors R1-R5 Composed in series, the resistance values ​​of multiple resistors in series and the design value rbody for the radio frequency resistance, the distributed capacitance network 20 is composed of 4 capacitors C1-C4 with equal capacitance, the capacitance of each capacitor is cox / 4, and cox is the radio frequency The total capacitance of the resistance buried oxide layer (Buried ...

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Problems solved by technology

[0003] exist figure 1 There is a capacitive path in , that is, the first distributed capacitance C1 to the last distributed capacitance C4, and the simulation is performed according to this model, such as figure 2 As shown, it is obvious from the simulation results that as the frequency increases, the model shows that the impedance of the RF resistor decreases significantly, which is inconsistent with the SOI process

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