Three-dimensional storage and manufacturing method thereof
A manufacturing method and memory technology, applied in the direction of electric solid-state devices, semiconductor devices, electrical components, etc., can solve the problem of wasting three-dimensional memory area and achieve the effect of reducing the area
Active Publication Date: 2019-04-09
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
[0005] The current partition design will generate invalid areas at both ends of the ladder direction of the independent partition, wasting the area of the 3D memory
Method used
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[0038] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.
[0039] In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways than those described here, so the present invention is not limited by the specific embodiments disclosed below.
[0040] As indicated in this application and claims, the terms "a", "an", "an" and / or "the" do not refer to the singular and may include the plural unless the context clearly indicates an exception. Generally speaking, the terms "comprising" and "comprising" only suggest the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list, and the method or device may also contain other st...
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The invention relates to a three-dimensional storage and a manufacturing method thereof. The method comprises the steps of forming a first mask pattern on a stair area of a semiconductor structure, wherein the first mask pattern comprises a first mask layer corresponding to a partitioned stair structure area of the stair area, and the width of the first mask layer in a second direction is not morethan the widths of two stairs; forming an initial stair around the first mask layer by using the first mask pattern; removing the first mask pattern; forming a second mask pattern on the stair area,wherein the second mask pattern comprises a second mask layer corresponding to the partitioned stair structure area, the two opposite edges of the second mask layer along a first direction is in flushwith the two opposite edges of the first mask layer along the first direction, the two opposite edges of the second mask layer along a second direction are separately more than the two opposite edgesof the first mask layer along the second direction by the widths of the N stairs, and N is not less than 2; and by using the second mask pattern, forming a first set of stairs on two sides of the second mask layer along the first direction, and forming a second set of stairs on the two sides along the second direction.
Description
technical field [0001] The invention mainly relates to a semiconductor manufacturing method, in particular to a three-dimensional memory and a manufacturing method thereof. Background technique [0002] In order to overcome the limitations of two-dimensional memory devices, the industry has developed memory devices with a three-dimensional (3D) structure to increase integration density by three-dimensionally arranging memory cells on a substrate. [0003] In a three-dimensional memory such as 3D NAND flash memory, the memory array may include a core region and a stair region. The stepped area is used to lead out contacts for the control gates in each layer of the memory array. These control gates are used as word lines of the memory array to perform operations such as programming, erasing and writing, and reading. [0004] The stepped area typically uses a unidirectional stepped structure. As the number of layers of the three-dimensional memory increases, the unidirection...
Claims
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Login to View More IPC IPC(8): H01L27/11551H01L27/11578
CPCH10B41/20H10B43/20
Inventor 华文宇夏志良吕震宇
Owner YANGTZE MEMORY TECH CO LTD