Adaptive broadband phase-locked loop circuit

Abstract

The invention relates to an adaptive broadband phase-locked loop circuit, comprising an adaptive driver, a first voltage-current converter, a charge pump and a loop filter. The adaptive driver accumulates phase difference of an output clock of a phase-locked loop and a reference clock, thereby obtaining a rough adjustment control voltage, and outputs the rough adjustment control voltage to the first voltage-current converter. The first voltage-current converter converts the rough adjustment control voltage into a rough adjustment control current. The charge pump takes a mirror current of the rough adjustment control current as a current source, pumps charges into the loop filter or pumps the charges out from the loop filter according to an advancing phase difference signal UP and a laggingphase difference signal DOWN of the output clock through comparison with the input reference clock, and outputs a control voltage signal VCTRL of a voltage-controlled oscillator. According to the phase-locked loop circuit provided by the invention, an output frequency range of the phase-locked loop is expanded, and capture time is reduced. The phase-locked loop circuit can be applied to a clock circuit of a high speed analog-to-digital converter and a high speed serial interface circuit.

Description

technical field [0001] The invention relates to an adaptive broadband phase-locked loop circuit, which belongs to the technical field of integrated circuits and is mainly used to generate a high-speed broadband stable clock. The circuit adjusts the loop bandwidth through an adaptive drive module, shortens the locking time, and is a high-speed serial interface. Provide the clock to ensure the accurate transmission of high-speed data. Background technique [0002] The significance of the phase-locked loop circuit is that it can flexibly give clock signals of various frequencies according to a reference clock signal. Although the crystal oscillator circuit can be used to generate frequency signals in some applications, its inflexibility in adjusting the frequency, the high cost of outputting high-frequency signals, and the speed of the chip interface all limit its application in integrated circuits. The phase-locked loop circuit can provide multiple frequency multiplied signal...

AI Technical Summary

Problems solved by technology

[0005] Fixed bandwidth PLLs have drawbacks, such as choosing a lower bandwidth, which will result in longer acquisition time or larger chip area; when the PLL operating conditions change, the fixed bandwidth value makes the PLL unable to suppress more Noise interference; fixed PLL parameters are easily affected by process, power supply voltage and temperature changes, making the final parameters of the PLL deviate from the design value; in addition, the fixed bandwidth PLL has high circuit cost

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