This invention relates to the field of
analog circuit design technology and discloses a method for anomaly identification and
feature selection of multi-source heterogeneous data. It involves generating and optimizing a custom multi-parameter, multi-constraint circuit topology within an analog circuit environment, using an analog
integrated circuit netlist as
graph theory input. This method uses a multi-constraint custom circuit, taking an initial circuit structure as
graph theory input, predicting the size of the analog
integrated circuit using maximum likelihood
estimation, and updating the simulated
netlist as the
graph theory input. Through comparison, the size is continuously updated, ultimately achieving automatic generation of the circuit structure from the desired structure to the final structure. Through state observation, a graph neural
network model is used to optimize the circuit topology, ultimately outputting a highly feasible circuit topology whose performance parameters can reach or even surpass those of manually designed analog integrated circuits.