IDFT-based software phase-locked loop implementation method and device

Abstract

The invention discloses an IDFT-based software phase-locked loop method and device. Voltage signals of a non-ideal three-phase system are sampled to transform a three-phase network voltage from an abcstationary coordinate system to a [alpha][beta] stationary coordinate system through clarke transform, voltage fundamental positive sequence signals are extracted through the IDFT, and the voltage signals in the [alpha][beta] stationary coordinate system are transformed to a dq synchronous rotating coordinate system through park transform. The angular frequency of voltage fundamental wave positive sequence signals is obtained by a PI controller. The device comprises a sampling unit, a phase locking ring unit, a closed loop control unit, a sinusoidal pulse width modulation unit, a drive unit and an NPC three-level inverter. The method can filter the harmonic component, the negative sequence component and the direct current component of the non-ideal network voltage signal in the two-phasestationary coordinate system, and is simple in design of the phase-locked loop parameters and high in phase-locking precision.

Description

technical field [0001] The invention relates to the technical field of power electronic conversion, in particular to an IDFT-based software phase-locked loop realization method and device. Background technique [0002] Synchronization to a reference signal is important in new energy applications, such as distributed generation, where grid-connected converters must typically be synchronized with the phase and frequency of the utility grid. A Phase Locked Loop (PLL) can be used to synchronize with the signal. For example, Single Synchronous Reference Frame Software Phase Lock Loop (Single Synchronous Reference Frame Software Phase Lock Loop—SSRF-PLL) is a widely used PLL technology, which can detect the phase angle and frequency of a reference signal. Under certain conditions, SSRF-PLL can quickly and accurately detect the phase angle, fundamental frequency and amplitude of the reference signal. If the reference signal is distorted due to low-order harmonics, the influence o...

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Problems solved by technology

Cascade Delayed Signal Cancellation Software Phase Locked Loop (Cascade Delayed Signal Cancellation Software Phase Locked Loop—CDSC-SPLL) based on cascade delay signal cancellation method, and apply cascade delay cancellation method to filter out all harmonic components on the basis of SSRF-PLL phase locked loop , so as to extract the voltage positive sequence component to lock the fundamental wave phase and frequency of the power grid, but in the digital system, the signal is discontinuous, and the delay signal error is inevitable. Algorithms such as weighted average can be used to reduce the error, but the five-level modules need to be calculated separately , a large amount of calculation

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