IDFT-based software phase-locked loop implementation method and device

A technology of software phase-locked loop and implementation method, which is applied in the direction of single-network parallel feeding arrangement, etc., can solve the problems of signal discontinuity, delay signal error, large calculation amount, etc., and achieve easy digital implementation, troubleshooting influence, calculation volume streamlining effect

Active Publication Date: 2019-04-19
HEFEI KEWELL POWER SYST CO LTD
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

Cascade Delayed Signal Cancellation Software Phase Locked Loop (Cascade Delayed Signal Cancellation Software Phase Locked Loop—CDSC-SPLL) based on cascade delay signal cancellation method, and apply cascade delay cancellation method to filter out all harmonic components on the basis of SSRF-PLL phase locked loop , so as to extract the voltage posi

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  • IDFT-based software phase-locked loop implementation method and device
  • IDFT-based software phase-locked loop implementation method and device
  • IDFT-based software phase-locked loop implementation method and device

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Embodiment 1

[0105] The implementation method of the software phase-locked loop based on IDFT in this embodiment comprises the following steps:

[0106] Step 1. Combine the attached figure 1 , image 3 , in the nth switching cycle, the voltage signal u a (n), u b (n), u c (n) Convert to the αβ static coordinate system through the clark transformation to get u α (n), u β (n), the conversion formula is as follows:

[0107]

[0108] where u a (n) is the phase A voltage sampling signal of the nth switching cycle, u b (n) is the B-phase voltage sampling signal of the nth switching cycle, u c (n) is the phase C voltage sampling signal of the nth switching cycle.

[0109] Step 2, put u α (n), u β (n) Extract the quasi-fundamental positive sequence signal u by Inverse Discrete Fourier Transform 1 (Inverse Discrete FourierTransform 1, IDFT1) α '(n), u β '(n); put u α (n), u β (n) Extract the quasi-fundamental positive sequence signal u through Inverse Discrete Fourier Transform 2 ...

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Abstract

The invention discloses an IDFT-based software phase-locked loop method and device. Voltage signals of a non-ideal three-phase system are sampled to transform a three-phase network voltage from an abcstationary coordinate system to a [alpha][beta] stationary coordinate system through clarke transform, voltage fundamental positive sequence signals are extracted through the IDFT, and the voltage signals in the [alpha][beta] stationary coordinate system are transformed to a dq synchronous rotating coordinate system through park transform. The angular frequency of voltage fundamental wave positive sequence signals is obtained by a PI controller. The device comprises a sampling unit, a phase locking ring unit, a closed loop control unit, a sinusoidal pulse width modulation unit, a drive unit and an NPC three-level inverter. The method can filter the harmonic component, the negative sequence component and the direct current component of the non-ideal network voltage signal in the two-phasestationary coordinate system, and is simple in design of the phase-locked loop parameters and high in phase-locking precision.

Description

technical field [0001] The invention relates to the technical field of power electronic conversion, in particular to an IDFT-based software phase-locked loop realization method and device. Background technique [0002] Synchronization to a reference signal is important in new energy applications, such as distributed generation, where grid-connected converters must typically be synchronized with the phase and frequency of the utility grid. A Phase Locked Loop (PLL) can be used to synchronize with the signal. For example, Single Synchronous Reference Frame Software Phase Lock Loop (Single Synchronous Reference Frame Software Phase Lock Loop—SSRF-PLL) is a widely used PLL technology, which can detect the phase angle and frequency of a reference signal. Under certain conditions, SSRF-PLL can quickly and accurately detect the phase angle, fundamental frequency and amplitude of the reference signal. If the reference signal is distorted due to low-order harmonics, the influence o...

Claims

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Application Information

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IPC IPC(8): H02J3/44
CPCH02J3/44
Inventor 赵涛
Owner HEFEI KEWELL POWER SYST CO LTD
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