A DRAM output driving circuit and a method for reducing electric leakage thereof

Abstract

The DRAM output driving circuit comprises a pull-up transistor and a pull-down transistor which are sequentially connected to a working voltage end and a grounding voltage end, and a driving voltage output end dq is arranged between the pull-up transistor and the pull-down transistor; wherein the substrate of the pull-up transistor is connected with the output end of the voltage selector, the input end of the voltage selector is respectively connected with corresponding loading voltage and additional loading voltage, and the control end of the voltage selector is connected with a voltage selection signal. The voltage selector is arranged to aim at different pull-up transistors; Substrate voltages of different sizes are selected under different states, so that the leakage current of the output driving circuit can be reduced in a power-saving mode according to the correlation between the leakage current of different pull-up transistors and threshold voltage, the electric leakage is reduced, and enough driving capability can be provided for an output stage under the condition of normal work; and the leakage current of the DRAM output driving circuit in a power-saving mode is effectively reduced.

Description

technical field [0001] The invention relates to a DRAM output driving circuit, in particular to a DRAM output driving circuit and a method for reducing electric leakage. Background technique [0002] In the prior art, the output driver circuit of the DRAM memory includes the following two types according to the type of the pull-up transistor: one is when the pull-up transistor is PMOS, that is, P1, such as figure 1 shown. In the power saving mode of DRAM, the dq pin is connected to gnd, and the connection state of PMOS is: vb=vdd; power saving mode: dat_pu=vdd, data_pd=gnd, dq=gnd; although P1 does not have when vsg=0v It is turned on, and there is still leakage from vdd to dq, which is determined by the device characteristics, where vsg refers to the source and gate voltage difference of P1. The other is when the pull-up transistor is NMOS, namely N1, such as figure 2 shown. In the power saving mode of DRAM, the dq pin is connected to gnd, and the connection state of N...

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Problems solved by technology

However, in the low power circuit design, the leakage of the device in the off state needs to be considered. Therefore, in the power saving mode of the DRAM memory in the prior art, the leakage of the output stage driving circuit is too large to meet the actual requirements. Require

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