Fan-out type packaging structure and packaging method of chip

Abstract

The invention discloses a fan-out type packaging structure and packaging method of a chip; the fan-out type packaging structure comprises a first chip, a second chip, a plurality of metal terminals, alead, a packaging layer, and an extraction layer; the bottom surface of the first chip and the bottom surface of the second chip are oppositely attached to each other; the plurality of metal terminals are distributed on the periphery of the first chip, one face of the metal terminal is located on the same plane as the front surface of the first chip; the lead is connected between the front face of the second chip and the other face of the metal terminal; the packaging layer is used for packaging the first chip, the second chip, the lead and the metal terminals; and the extraction layer is arranged on a first surface of the packaging layer and is respectively electrically connected with one face of the metal terminal and / or the front face of the first chip. Compared with the fan-out type packaging structure packaged by using a slide glass whole surface, a plurality of metal terminals are arranged in a distributed mode, the packaging structure is balanced by utilizing the volume ratio of the metal terminals, for example, the numerical value of the equivalent thermal expansion coefficient of the packaging body is reduced, so that warping of the product is controlled, and packaging deformation warping is reduced. In addition, signal interconnection of multi-chip stacked in the Z direction can be realized through the plurality of metal terminals.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a chip fan-out packaging structure and packaging method. Background technique [0002] In the chip packaging process in the prior art, such as the fan-out packaging structure, it is a manually reconstructed wafer, and the reconstructed wafer contains plastic, silicon and metal materials, and the volume edge sum and thermal expansion coefficient between silicon and plastic The difference in each direction of X, Y, and Z will cause the warpage of the package due to thermal expansion and contraction when the process is heated and cooled. Contents of the invention [0003] Therefore, the present invention provides a chip fan-out packaging structure, which reduces the warpage of the packaging body. [0004] According to the first aspect, an embodiment of the present invention provides a chip fan-out packaging structure, at least including: a first chip and a second ...

AI Technical Summary

Problems solved by technology

[0002] In the chip packaging process in the prior art, such as the fan-out packaging structure, it is a manually reconstructed wafer, and the reconstructed wafer contains plastic, silicon and metal materials, and the volume edge sum and thermal expansion coefficient between silicon and plastic The difference in each direction of X, Y, and Z will lead to the warpage of the package due to thermal expansion and contraction when the process is heated and cooled

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