A single pulse generation circuit and a bidirectional level conversion circuit

[0044] As described in the background art, in the existing level conversion chip, the pull-up control module will cause the chip to consume more power. Such as figure 1 As shown, figure 1 It is a schematic structural diagram of an existing level conversion chip. When the first terminal A of the signal transmission terminal MN turns from low level to high level, the second control module controls the second pull-up tube MP2 to be turned on, and the signal The second terminal B of the transmission terminal MN is pulled from low to high; when the second terminal B of the signal transmission terminal MN turns from low to high, the first control module controls the first pull-up tube MP1 to conduct On, the first terminal A of the signal transmission terminal MN is pulled from low level to high level.

[0045] Such as figure 2 As shown, figure 2 It is a schematic diagram of the structure of an existing control module. When the first terminal A or the second terminal B is turned from low level to high level, the B1 node passes through the filter network formed by the resistor R0 and the capacitor C0 to generate a high to low The delay signal of node B2 and node B1 are in-phase signals, and a delay signal from high to low is also generated. Therefore, for the AND unit D1, the output will be high during the delay t≈R0*C0 Therefore, the output terminal LOUT will output a low level signal within the pulse width t to accelerate the opening of the pull-up tube MP1 or MP2.

[0046] However, due to the fixed time of the low-level signal, in the application, if the level of the pull-up port B or A flips to a high level within the pulse width t, and the control module will not recognize the port level, it will still Maintaining a strong pull-up state, therefore, will cause the pull-up tube to be continuously turned on, resulting in an increase in the power consumption of the circuit, and destroying the impedance matching and signal integrity of the output port.

[0047] Based on this, the present invention provides a single pulse generating circuit to overcome the above-mentioned problems in the prior art, including a first signal input terminal, a second signal input terminal, a port detection module, and a single pulse generating module;

[0048] The first input end of the port detection module is electrically connected to the first signal input end, the second input end of the port detection module is electrically connected to the second signal input end, and the output end of the port detection module It is electrically connected to the first input terminal of the single pulse generation module, and the port detection module is configured to output a high level when at least one of the first signal input terminal and the second signal input terminal is low level When the first signal input terminal and the second signal input terminal are both at a high level, output a low level, so that the output of the single pulse generation module is accelerated to flip to a high level;

[0049] The second input terminal of the single pulse generating module is electrically connected with the first signal input terminal, the third input terminal of the single pulse generating module is electrically connected with the second signal input terminal, and the single pulse generating module It is used to output a low-level pulse when either end of the first signal input terminal and the second signal input terminal is turned from low level to high level.

[0050] In the single pulse generating circuit provided by the present invention, when either end of the first signal input terminal and the second signal input terminal is turned from low level to high level, the single pulse generating module outputs a low level pulse to control the pull-up tube guide Pass, when both ends of the first signal input terminal and the second signal input terminal are turned to high level, the port detection module outputs a low level, so that the output of the single pulse generation module is quickly turned from a low level pulse to a high level , In order to control the pull-up tube to turn off, thereby reducing power consumption and ensuring the impedance matching and signal integrity of the output port.

[0051] The above is the core idea of ​​the present invention. In order to make the above objectives, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Description, obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

[0052] The embodiment of the present invention provides a single pulse generating circuit, such as image 3 As shown, it includes a first signal input terminal LA, a second signal input terminal LB, a port detection module and a single pulse generation module;

[0053] Wherein, the first input end of the port detection module is electrically connected to the first signal input end LA, the second input end of the port detection module is electrically connected to the second signal input end LB, and the output end of the port detection module is electrically connected to the single pulse generation module. The first input terminal is electrically connected, and the port detection module is used for outputting a low level when the first signal input terminal LA and the second signal input terminal LB are both at a high level, at the first signal input terminal LA and the second signal input terminal When at least one end of LB is low, the output is high.

[0054] The second input end of the single pulse generation module is electrically connected to the first signal input end LA, the third input end of the single pulse generation module is electrically connected to the second signal input end LB, and the single pulse generation module is used for the first signal input end When either end of LA and the second signal input terminal LB turns from low level to high level, a low level pulse is output. The single pulse generation module is also used to accelerate the transition of the output from the low level pulse to the high level when the output of the port detection module changes from high level to low level.

[0055] Such as image 3 As shown, the port detection module includes a NAND gate NA1 and a first inverter NV1 to a fourth inverter NV4; the input terminal of the first inverter NV1 is electrically connected to the first signal input terminal LA, and the second inverter The input end of NV2 is electrically connected to the output end of the first inverter NV1, the output end of the second inverter NV2 is electrically connected to an input end of the NAND gate NA1; the input end of the third inverter NV3 is electrically connected to the second The signal input terminal LB is electrically connected, the input terminal of the fourth inverter NV4 is electrically connected with the output terminal of the third inverter NV3, and the output terminal of the fourth inverter NV4 is electrically connected with the other input terminal of the NAND gate NA1 Wherein, the input end of the first inverter NV1 is electrically connected to the first input end of the port detection module, the input end of the third inverter NV3 is electrically connected to the second input end of the port detection module, and the NAND gate NA1 The output terminal is electrically connected to the output terminal A1 of the port detection module.

[0056] The single pulse generation module includes a first transistor M1 to a third transistor M3, a first resistor R1, a second resistor R2, a fifth inverter NV5 to a seventh inverter NV7, a first NOR gate NOR1, and a second NOR gate. Gate NOR2. One input terminal of the first NOR gate NOR1 is electrically connected to the first signal input terminal LA, the other input terminal of the first NOR gate NOR1 is electrically connected to the second signal input terminal LB, and the output terminal of the first NOR gate NOR1 A2 is electrically connected to the gate of the first transistor M1; the first end of the first transistor M1 is electrically connected to the power supply terminal VA, and the second end of the first transistor M1 is electrically connected to one end of the first resistor R1. The other end is electrically connected to one end of the second resistor R2, the other end of the second resistor R2 is electrically connected to the first end of the second transistor M2, the second end of the second transistor M2 is electrically connected to the ground terminal GND, and the second transistor M2 The gate of the third transistor M3 is electrically connected to the output end of the first NOR gate NOR1; the gate of the third transistor M3 is electrically connected to the output end A1 of the port detection module, and the first end of the third transistor M3 is electrically connected to one end of the first resistor R1. Connected, the second end of the third transistor M3 is electrically connected to the other end of the first resistor R1; the input end of the fifth inverter NV5 is electrically connected to the other end of the second resistor R2, and the output end of the fifth inverter NV5 It is electrically connected to the input terminal of the sixth inverter NV6, the output terminal of the sixth inverter NV6 is electrically connected to an input terminal of the second NOR gate NOR2, and the output terminal of the first NOR gate NOR1 is electrically connected to the second NOR gate. The other input terminal of the gate NOR2 is electrically connected, the output terminal of the second NOR gate NOR2 is electrically connected with the input terminal of the seventh inverter NV7, and the output terminal of the seventh inverter NV7 is electrically connected with the output terminal LOUT of the single pulse generation module Electric connection.

[0057] Among them, the first transistor M1 and the third transistor M3 are PMOS transistors, and the second transistor M2 is an NMOS transistor. Of course, the present invention is not limited to this. In other embodiments, the first transistor M1 and the third transistor M3 may also be NMOS transistors, and the second transistor M2 may also be PMOS transistors.

[0058] reference image 3 with Figure 4 When the first signal input terminal LA and the second signal input terminal LB are both at high level, the output terminal A1 of the port detection circuit outputs low level, the output terminal A2 of the first NOR gate NOR1 outputs low level, and the second The transistor M2 is turned off, the first transistor M1 and the third transistor M3 are turned on, the nodes A3 and A4 are pulled up to a high level, and the output terminal LOUT outputs a high level.

[0059] When the first signal input terminal LA and the second signal input terminal LB are at low level, the output terminal A1 outputs high level, the third transistor M3 is turned off, and the output terminal A2 outputs high level, so that the first transistor M1 is turned off, The second transistor M2 is turned on and pulls down the nodes A3 and A4 to a low level, so that the output terminal LOUT outputs a high level.

[0060] When either end of the first signal input terminal LA and the second signal input terminal LB flips from low to high, for example, when the first signal input LA flips from low to high, the output terminal A1 still outputs high Level, the third transistor M3 remains off, and the output terminal A2 outputs a low level, so that the first transistor M1 is turned on and the second transistor M2 is turned off, and the node A3 will turn from low to high. However, because At this time, the current will be limited by the first resistor R1 and the second resistor R2, causing the node A3 to have a delay, so that the node A4 will turn from the low level to the high level and there will also be a delay. Therefore, the output terminal LOUT will output a certain amount Low-level pulse of time period t. Among them, t=(R1+R2)*C, C is the parasitic capacitance of node A3.

[0061] And, after t time, the nodes A3 and A4 are inverted to a high level, and the output terminal LOUT outputs a high level. In addition, when the second terminal B connected to the second signal input terminal LB is pulled to a high level at t1, t1 is less than t, the output terminal A1 flips to a low level, and the third transistor M3 is turned on, so that the flow The current of the first transistor M1 increases, so that the output terminal LOUT can be flipped to a high level in advance, and there is no need to wait for t-t1 before flipping to a high level.

[0062] will image 3 When the single pulse generating circuit shown is applied to the level conversion circuit to control the pull-up tube, please refer to Image 6 , The first signal input end LA is electrically connected to the first end A of the signal transmission tube, and the second signal input end LB is electrically connected to the second end B of the signal input tube. When either end of the first end A or the second end B is When flipping from low level to high level, such as when the first terminal A flips from low level to high level, the first signal input terminal LA flips from low level to high level, and the output terminal of the single pulse generation module is the single The output terminal LOUT of the pulse generating circuit will output a low-level pulse for a certain period of time t, control the pull-up tube MP1 and MP2 to turn on, pull the other end, the second end B, to a high level, and when the other end is After the second terminal B is pulled up to a high level, the port detection module outputs a low level, which makes the output terminal LOUT of the single pulse generating circuit flip to a high level in advance, and controls the pull-up tube MP1 and MP2 to turn off, thereby reducing Power consumption to ensure impedance matching and signal integrity of the port.

[0063] In another embodiment of the present invention, such as Figure 5 As shown, the port detection module includes an AND gate NA2 and a first inverter NV1 to a fourth inverter NV4; the input terminal of the first inverter NV1 is electrically connected to the first signal input terminal LA, and the second inverter NV2 The input terminal of the first inverter NV1 is electrically connected to the output terminal of the second inverter NV2 and an input terminal of the AND gate NA2 is electrically connected; the input terminal of the third inverter NV3 is electrically connected to the second signal input The terminal LB is electrically connected, the input terminal of the fourth inverter NV4 is electrically connected with the output terminal of the third inverter NV3, and the output terminal of the fourth inverter NV4 is electrically connected with the other input terminal of the AND gate NA2; wherein, The input terminal of the first inverter NV1 is electrically connected to the first input terminal of the port detection module, the input terminal of the third inverter NV3 is electrically connected to the second input terminal of the port detection module, and the output terminal of the AND gate NA2 is electrically connected to the port The output terminal A1 of the detection module is electrically connected.

[0064] The single pulse generation module includes a first transistor M1 to a third transistor M3, a first resistor R1, a second resistor R2, a fifth inverter NV5 to a seventh inverter NV7, a first NOR gate NOR1, and a second NOR gate. Gate NOR2; one input terminal of the first NOR gate NOR1 is electrically connected to the first signal input terminal LA, the other input terminal of the first NOR gate NOR1 is electrically connected to the second signal input terminal LB, the first NOR gate NOR1 The output terminal A2 of the first transistor M1 is electrically connected to the gate of the first transistor M1; the first terminal of the first transistor M1 is electrically connected to the power supply terminal VA, the second terminal of the first transistor M1 is electrically connected to one end of the first resistor R1, The other end of the resistor R1 is electrically connected to one end of the second resistor R2, the other end of the second resistor R2 is electrically connected to the first end of the second transistor M2, and the second end of the second transistor M2 is electrically connected to the ground terminal GND. The gate of the second transistor M2 is electrically connected to the output end of the first NOR gate NOR1; the gate of the third transistor M3 is electrically connected to the output end A1 of the port detection module, and the first end of the third transistor M3 is electrically connected to the second resistor R2 The second end of the third transistor M3 is electrically connected to the other end of the second resistor R2; the input end of the fifth inverter NV5 is electrically connected to the other end of the second resistor R2, and the fifth inverter NV5 The output terminal of the sixth inverter NV6 is electrically connected to the input terminal of the sixth inverter NV6, the output terminal of the sixth inverter NV6 is electrically connected to an input terminal of the second NOR gate NOR2, and the output terminal of the first NOR gate NOR1 is electrically connected to the first NOR gate NOR2. The other input end of the second NOR gate NOR2 is electrically connected, the output end of the second NOR gate NOR2 is electrically connected to the input end of the seventh inverter NV7, and the output end of the seventh inverter NV7 is electrically connected to the single pulse generation module The output terminal LOUT is electrically connected. Among them, the first transistor M1 is a PMOS transistor, and the second transistor M2 and the third transistor M3 are NMOS transistors.

[0065] When the first signal input terminal LA and the second signal input terminal LB are both high level, the output terminal A1 of the port detection circuit outputs high level, the output terminal A2 of the first NOR gate NOR1 outputs low level, and the second transistor M2 is turned off, the first transistor M1 and the third transistor M3 are turned on, the nodes A3 and A4 are pulled up to a high level, and the output terminal LOUT outputs a high level.

[0066] When the first signal input terminal LA and the second signal input terminal LB are at low level, the output terminal A1 outputs low level, the third transistor M3 is turned off, and the output terminal A2 outputs high level, so that the first transistor M1 is turned off, The second transistor M2 is turned on and pulls down the nodes A3 and A4 to a low level, so that the output terminal LOUT outputs a high level.

[0067] When either end of the first signal input terminal LA and the second signal input terminal LB is turned from low level to high level, for example, when the first signal input terminal LA is turned from low level to high level, the output terminal A1 still outputs low Level, the third transistor M3 remains off, and the output terminal A2 outputs a low level, so that the first transistor M1 is turned on and the second transistor M2 is turned off, and the node A3 will switch from low level to high level. However, because At this time, the current will be limited by the first resistor R1 and the second resistor R2, causing the node A3 to have a delay, so that the node A4 will turn from the low level to the high level and there will be a delay. Therefore, the output terminal LOUT will output a certain amount Low-level pulse of time period t. Among them, t=(R1+R2)*C, C is the parasitic capacitance of node A3.

[0068] And, after t time, the nodes A3 and A4 are inverted to a high level, and the output terminal LOUT outputs a high level. In addition, when the second terminal B connected to the second signal input terminal LB is pulled to a high level at t1, t1 is less than t, the output terminal A1 flips to a high level, and the third transistor M3 is turned on, making the flow The current of the first transistor M1 increases, so that the output terminal LOUT can be flipped to a high level in advance, and there is no need to wait for t-t1 before flipping to a high level.

[0069] will Figure 5 When the single pulse generating circuit shown is applied to the level conversion circuit to control the pull-up tube, please refer to Image 6 , The first signal input end LA is electrically connected to the first end A of the signal transmission tube, and the second signal input end LB is electrically connected to the second end B of the signal input tube. When either end of the first end A or the second end B is When flipping from low level to high level, such as when the second terminal B flips from low level to high level, the second signal input terminal LB flips from low level to high level, and the output terminal of the single pulse generation module is the single The output terminal LOUT of the pulse generating circuit will output a low-level pulse for a certain period of time t, control the pull-up tubes MP1 and MP2 to conduct, and pull the other end, the first end A, to a high level, and when the other end is After the first terminal A is pulled up to a high level, the port detection module outputs a low level, so that the output terminal LOUT of the single pulse generating circuit flips to a high level in advance, and controls the pull-up tube MP1 and MP2 to turn off, thereby reducing Power consumption to ensure the impedance matching and signal integrity of the port.

[0070] The embodiment of the present invention also provides a bidirectional level conversion circuit, such as Image 6 As shown, the signal transmission tube, the first pull-up tube, the second pull-up tube and the single pulse generating circuit, the single pulse generating circuit is the single pulse generating circuit provided in any of the above embodiments;

[0071] The first end of the first pull-up tube is electrically connected to the first voltage terminal, the second end of the first pull-up tube is electrically connected to the first end of the signal transmission tube, and the first end of the second pull-up tube is electrically connected to the second voltage The second end of the second pull-up tube is electrically connected to the second end of the signal transmission tube; the first signal input end of the single pulse generating circuit is electrically connected to the first end of the signal transmission tube, and the single pulse generating circuit The second signal input terminal is electrically connected with the second terminal of the signal transmission tube, and the output terminal of the single pulse generating circuit is electrically connected with the grids of the first pull-up tube and the second pull-up tube.

[0072] Among them, when the first pull-up tube MP1 and the second pull-up tube MP2 are PMOS transistors, the first level is low, and when the first pull-up tube MP1 and the second pull-up tube MP2 are NMOS transistors, the first level is low. One level is high. In the embodiment of the present invention, only the first pull-up tube MP1 and the second pull-up tube MP2 are PMOS transistors, and the signal transmission tube MN is an NMOS transistor as an example for description.

[0073] It should be noted that such as Image 6 As shown, the bidirectional level conversion circuit in the embodiment of the present invention further includes a driving circuit; the driving circuit is used to control the signal transmission tube MN to be turned on when both ends of the signal transmission tube MN are at the first level. Specifically, when the signal transmission tube MN is an NMOS transistor, the driving circuit is used to control the signal transmission tube MN to be turned on when both ends of the signal transmission tube MN are low, and both ends of the signal transmission tube MN are high. At the level, the control signal transmission tube MN is disconnected.

[0074] In other words, in the bidirectional level conversion circuit in the embodiment of the present invention, when the first end A and the second end B are both low, the control signal transmission tube MN is turned on to realize the transmission of two voltage domain signals. When either one of the first terminal A and the second terminal B is at a high level, the first pull-up tube MP1 or the second pull-up tube MP2 is controlled to be turned on, and the other end is pulled up to a high level to realize two voltage domain signals Transmission.

[0075] In the single pulse generating circuit and the bidirectional level conversion circuit provided by the present invention, when either end of the first signal input terminal and the second signal input terminal is turned from low level to high level, the single pulse generating module outputs a low level pulse , To control the conduction of the pull-up tube, when both ends of the first signal input terminal and the second signal input terminal are turned to high level, the port detection module outputs low level, so that the output of the single pulse generation module changes from low level The pulse speeds up the flip to a high level to control the pull-up tube to turn off, thereby reducing power consumption and ensuring the impedance matching and signal integrity of the output port. Moreover, since the single pulse generating circuit provided by the embodiment of the present invention does not need to integrate the delay capacitor C0, the area and cost will be reduced.

[0076] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0077] The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined in this document can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown in this document, but should conform to the widest scope consistent with the principles and novel features disclosed in this document.