A kind of erasing enhanced nord flash memory and preparation method thereof

Abstract

The invention discloses an erasure enhanced NORD flash memory and a preparation method thereof. Erasing enhanced NORD flash memory includes: a silicon-based substrate, on which adjacent first floating gate regions and second floating gate regions are arranged, and a coupling oxide layer, a floating gate polysilicon layer, and an electrode are sequentially deposited longitudinally from bottom to top. an interlayer dielectric layer, a control gate polysilicon layer, a floating gate spacer, and a displacement sidewall silicon oxide layer, which is sequentially provided on the adjacent sides of the first floating gate region and the second floating gate region away from the word line polysilicon layer. The sidewall silicon nitride layer is displaced and the oxide layer is tunneled. Among them, the word line polysilicon layer located at the top corner of the floating gate polysilicon layer is arranged in a surrounding "cross" structure. The word line polysilicon layer at the top corner of the floating gate polysilicon layer of the present invention is arranged in a surrounding "cross" structure, which enhances the electric field intensity between the floating gate polysilicon layer and the word line polysilicon layer, greatly improving the erasing performance. At the same time, the "ten" structure is producible and applicable, and is worthy of promotion and use by the industry.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an erasing enhanced NORD flash memory and a preparation method thereof. Background technique [0002] Due to its advantages of high density, low price, and electrical programmability and erasability, flash memory has been widely used as the best choice for non-volatile memory applications. Generally speaking, floating-gate flash memories have similar original cell structures, and they all have a stacked gate structure, which includes a floating gate and a control gate covering at least the floating gate. Wherein, the control gate is coupled to control storage and release of electrons in the floating gate. [0003] Nord flash memory erasing occurs through Fowler Nordheim (FN) tunneling between the floating gate (Floating Gate, FG) and the word line (Word Line, WL), through the tunneling between the word line and the control gate ( Control Gate (CG) applies hi...

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Problems solved by technology

[0006] The present invention is aimed at the prior art, the shape of the top angle of the existing floating gate has a great influence on the electric field of the tunneling oxide layer in the erasing area, and the blunt top angle of the floating gate will inevitably reduce the electric field intensity, making the erasing performance worse Inferior defects provide an erase-enhanced NORD flash

[0007] Another object of the present invention is to aim at the prior art, the shape of the existing floating gate apex has a great influence on the electric field of the tunneling oxide layer in the erasing region, and the relatively blunt floating gate apex will certainly reduce the electric field intensity, so that Defects such as poor erasing performance provide a preparation method for erasing enhanced NORD flash memory

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