An FPGA verification method of a JESD204B controller

Abstract

The invention relates to a JESD204B controller verification method. The JESD204B controller verification method comprises the following steps: (1-1) establishing a sending verification link from a sending end of a to-be-verified JESD204B controller to a reference receiving module; (1-2) establishing a receiving verification link from the reference sending module to the receiving end of the JESD204B controller to be verified; (1-3) carrying out link layer verification, verifying link code group synchronization of the JESD204B controller to be verified, and verifying whether an initialized channel alignment function is correct or not; (1-4) carrying out transmission layer verification, and verifying whether the link configuration data of the JESD204B controller to be verified is consistent with a JESD204B protocol and whether the mapping function of the sampling data and the frame data is correct or not; And (2-1) after the logic function simulation verification is passed, downloading codes of a sending end and a receiving end of the JESD204B controller to be verified into the FPGA corresponding to the sending verification system to complete board-level actual measurement verification. According to the JESD204B controller verification method, the JESD204B controller application condition is simulated by combining simulation and upper plate debugging, and the completeness and theaccuracy of JESD204B controller verification are improved.

Description

technical field [0001] The invention relates to an FPGA verification method and process of digital integrated circuit RTL-level source codes, in particular to an FPGA verification method for a JESD204B controller, and belongs to the technical field of digital integrated circuit prototype verification and simulation. Background technique [0002] JESD204B is mainly used for high-speed data transmission protocol between ADC or DAC and FPGA. It can convert parallel data into high-speed serial data or convert high-speed serial data into parallel data. [0003] In April 2006, the initial version of JESD204B, JESD204, was released. This version describes a multi-gigabit serial data link between a converter and a receiver (typically an FPGA or ASIC). [0004] JESD204A was published in April 2008. The ability to support multiple aligned serial lanes under multiple converters has been added in this release. The channel data rate supported by this version is 312.5Mbps to 3.125Gbps,...

AI Technical Summary

Problems solved by technology

[0006] The JESD204B protocol has a transport layer, a link layer, an application layer, and a physical layer. The physical layer is a high-speed serial-to-parallel converter, which involves a digital-analog hybrid circuit. Its performance is closely related to the process and layout. Generally, tools are used for simulation verification. Board-Level Verification Using FPGAs

[0007] Existing JESD204B controllers have few verification technologies. Generally, software model function simulation is performed according to verification requirements. There is no dedicated hardware verification system and verification method that meets the protocol requirements.

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