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A high-efficiency floating-point FFT hardware accelerator design method based on mixed base operation

A hardware accelerator and design method technology, applied in complex mathematical operations and other directions, can solve problems such as low operation accuracy and limited data dynamic range, achieve high operation accuracy, moderate area and power consumption overhead, and reduce hardware and power consumption overhead Effect

Inactive Publication Date: 2019-05-28
TSINGHUA UNIV
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Problems solved by technology

This method solves the shortcomings of traditional fixed-point and block floating-point FFT calculations such as limited dynamic range and low calculation accuracy. It is used for spectrum analysis applications in the field of high-precision and high-dynamic-range data. It has a clear structure, flexible configuration, and certain versatility. and scalability

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  • A high-efficiency floating-point FFT hardware accelerator design method based on mixed base operation
  • A high-efficiency floating-point FFT hardware accelerator design method based on mixed base operation
  • A high-efficiency floating-point FFT hardware accelerator design method based on mixed base operation

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Embodiment Construction

[0025] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0026] The following describes a design method of a high-efficiency floating-point FFT hardware accelerator based on mixed-radix operations proposed by an embodiment of the present invention with reference to the accompanying drawings.

[0027] Such as figure 1 As shown, the high-efficiency floating-point FFT hardware accelerator design method based on mixed-radix operations of the present invention mainly includes three aspects: a cascaded pipeline FFT hardware accelerator architecture design based on mixed-radix operations, and...

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Abstract

The invention discloses a high-efficiency floating point FFT hardware accelerator design method based on mixed base operation. The method comprises the following steps of carrying out floating point FFT hardware acceleration operation through a mixed base operation FFT algorithm, configuring different butterfly operation units to execute different butterfly operations according to the point numberof FFT, and obtaining a cascade type pipeline FFT hardware accelerator architecture design result; optimizing the number of floating point adders for butterfly operation through a hybrid-base butterfly operation unit addition operator scheduling method, completing the implementation of optimized butterfly operation hardware, and obtaining a hybrid-base butterfly operation unit design result; andadopting the data caching unit to the design of a data caching unit scheduled by an addition operator of the hybrid butterfly operation unit, so that data caching among all stages of butterfly operations of the pipeline FFT hardware accelerator is realized, and a design result of an intermediate data caching unit is obtained. The method has the advantages of being high in calculation precision anddynamic range, fast in processing speed, lower in hardware cost and power consumption, flexible in configuration and the like.

Description

technical field [0001] The invention relates to the technical field of high-efficiency floating-point FFT hardware accelerator design, in particular to a high-efficiency floating-point FFT hardware accelerator design method based on mixed base operations. Background technique [0002] Fast Fourier transform (fast Fourier transform, FFT) is an effective tool for frequency domain analysis engineering, and has been widely used in the field of traditional digital signal processing. For example, the fixed-point arithmetic FFT with limited precision has been researched in the field of wireless communication for many years. and has been successfully applied. [0003] However, in recent years, with the development of scientific computing and high-precision image processing applications, the requirements for data processing accuracy of such applications have become more stringent, especially higher requirements for data dynamic range, calculation accuracy and error processing. Fixed...

Claims

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Application Information

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IPC IPC(8): G06F17/14
Inventor 李兆麟王明羽
Owner TSINGHUA UNIV
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