3D NAND memory and forming method thereof

Abstract

The invention discloses a 3D NAND memory and a forming method thereof, and the forming method comprises the steps: forming a dielectric layer covering a step structure; forming a plurality of pseudo-through holes in the dielectric layer and the step structure, and placing pseudo-through hole material layers in the pseudo-through holes, wherein the hardness of the pseudo-through hole material layers is greater than that of the dielectric layer; forming a plurality of gate isolation grooves in the dielectric layer and the step structure after the pseudo through hole material layers are formed; forming conductive semiconductor layers in the gate isolation grooves, wherein the surfaces of the conductive semiconductor layers are lower than the surface of the dielectric layer; and forming metallayers on the conductive semiconductor layers, wherein the metal layers are disposed in the gate isolation grooves. The method provided by the invention avoids the residual of the metal layer.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a 3D NAND memory and a forming method thereof. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the planar NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory is proposed. [0003] At present, the main components of 3D NAND memory can include array storage units and peripheral circuits, and the data access operations in each storage unit are realized through the control of peripheral circuits. Therefore, in the manufacturing process of 3D NAND memory, the conductance of each part Rate is an important link that cannot be ignored. [0004...

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Problems solved by technology

[0004] Among them, the Array Common Source (ACS for short) is an important structure requiring high conductivity. Currently, there are many schemes for forming the Array Common Source. In the first scheme, ACS is usually filled with tungsten (W). , although tungsten has good electrical conductivity, in the process of its formation, due to the large stress, it will cause various process problems, such as wafer warping and sliding, photolithography deformation, stacking dislocation, etc., which will lead to device pe

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