A configurable floating point vector multiplication ip core based on fpga

Abstract

The invention relates to a configurable floating point vector multiplication IP core based on an FPGA. The IP core comprises an operation controller, a multiplication array module and an addition array module. The operation controller is used for receiving the instruction signal, obtaining an input clock and outputting an RAM control signal and a state word to realize operation scheduling and instruction interaction; The multiplication array module is used for realizing multiplication of floating point vector elements, and the addition array module is used for realizing accumulation after multiplication of each element in the vector; The operation parallelism and the operation precision of the IP core are configurable, the flexibility and the universality are high, and the utilization rateof FPGA hardware resources is effectively improved; An operation controller is integrated, so that the problem of long design period of an FPGA-based calculation acceleration system is solved; The advantages of parallel operation and hardware reconfiguration of the FPGA are fully exerted, and parallel computing acceleration of the FPGA can be effectively realized; Especially under the condition that the current popular neural network calculation is not high in precision requirement but huge in calculation density, the arithmetic unit is reasonably configured according to the requirement, andthe resource utilization rate and the operation efficiency can be effectively improved.

Description

technical field [0001] The invention relates to the field of edge computing and parallel computing acceleration technologies, in particular to an FPGA-based configurable floating-point vector multiplication IP core. Background technique [0002] FPGA (Field-Programmable Gate Array), that is, field programmable gate array, is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates. As one of the main heterogeneous computing platforms at present, FPGA has the advantages of hardware reconfigurability, parallel operation and low power consumption, and is suitable for computing acceleration of embedded platforms. [0003] Taking vector multiplication as an example, two n-dimensional col...

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Problems solved by technology

[0011] At present, the floating-point vector multiplication operation IP core designed for FPGA has problems such as complex scheduling, fixed operation precision, and unconfigurable number of operators, which leads to long design cycle of FPGA-based computing acceleration system, waste of hardware resources, low energy efficiency ratio, and failure to achieve high performance. Computational Complexity Algorithm Requirements for Calculation Speed

[0012] Moreover, traditional FPGA-based floating-point vector multiplication accelerators mostly use IEEE754 standard single-precision (FP32) or double-precision (FP64) floating-point format operations, which cannot customize the calculation accuracy according to computing requirements, and do not take advantage of FPGA hardware reconfigurability

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