Defect-free filling method of silicon through electrode and copper plating solution used for the filling method

Abstract

An embodiment of the present invention provides a method for filling a through electrode, which includes the following steps: a step of immersing a through electrode having a through hole in a copper plating solution containing a leveling agent and a copper electrolyte; a first current applying step , applying a first current to coat the leveler on the upper side of the through hole of the through-electrode; a second current applying step, applying a second current lower than the first current, so that the forming a plating film of the copper electrolyte at the bottom of the through hole; a third current applying step, applying a third current higher than the first current, so that the copper electrolyte is filled from above the plating film of the copper electrolyte to the entrance of the through hole.

Description

technical field [0001] The present invention relates to an electroplating method for through-silicon electrodes, and more specifically relates to a method for filling through-silicon electrodes without defects (voids) in the process of filling the through-silicon electrodes with a plating solution containing a leveler. Background technique [0002] Since the initial stacked package uses metal wires to exchange electrical signals, the operation speed is slow, and because a large number of wires are used, the electrical characteristics of the stacked chips are degraded. In addition, the stacked package requires an additional area on the substrate for wire connection, so the overall size is large, and a gap (gap) for connecting wires is required between the stacked semiconductor chips, so the overall thickness is thick. [0003] In view of this, a package-on-package structure utilizing through electrodes has been proposed in order to overcome the problems of the package-on-pack...

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Problems solved by technology

[0004] In this regard, as a method of forming a through-hole electrode on a silicon substrate, according to Korean Laid-Open Patent Publication No. 10-2015-0099392 (hereinafter referred to as reference document 1), it is proposed to form a diffusion prevention layer on copper by electroless plating, and then laminate a copper seed layer. In order to fill TSVs with the method of reference 1, that is, the electroless plating method, it takes a long time to form the through-electrode, and the plating cannot be completely performed in the plating process, and there is a problem that defects occur, so it is necessary to adjust the power supply method

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