Inter-module flow control communication method based on combination of FIFO and random access memory

Abstract

The invention discloses an inter-module flow control communication method based on combination of FIFO and a random access memory, and belongs to the technical field of electronics. An FIFO input module, a calculation module, and an FIFO output module are established in the FPGA. The FIFO input module and the FIFO output module both comprise FIFO data buffers. The depth of the FIFO data buffer isset to be FIFO_Size. The width of the FIFO data buffer is set to be FIFO_Width, the FIFO data buffer is divided into N blocks, and one-time read-write data of the FIFO data buffer has the size as dataof one block size, so that the technical problem of carrying out data read-write operation by taking a block as a unit is solved, the data is cached, and the difference of data processing speeds among modules is solved; the method is suitable for an application scene where operation is carried out with a block as a unit, FIFO supports random reading and writing according to addresses, and variousreading and writing requirements are met.

Description

technical field [0001] The invention belongs to the field of electronic technology, in particular to a flow control communication method between modules based on the combination of FIFO and random access memory. Background technique [0002] In a communication system, data usually needs to be transmitted between two modules. If the data processing speed between the modules is the same, data transmission between the two modules can be performed directly. However, in FPGA design, the execution speed between the two modules is usually inconsistent. Data needs to be cached. In traditional communication systems, RAM is used for data caching, but RAM can only read and write bit by bit. When it needs to read and write blocks, RAM is not flexible enough. Contents of the invention [0003] The object of the present invention is to provide a flow control communication method between modules based on the combination of FIFO and random access memory, which solves the technical problem...

AI Technical Summary

Problems solved by technology

[0002] In a communication system, data usually needs to be transmitted between two modules. If the data processing speed between the modules is the same, data transmission between the two modules can be performed directly. However, in FPGA design, the execution speed between the two modules is usually inconsistent. Data needs to be cached. In traditional communication systems, RAM is used for data caching, but RAM can only be read and written bit by bit. When it needs to read and write blocks, RAM is not flexible enough.

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