A nand Flash Bit Error Rate Prediction Method Based on Support Vector Regression

Abstract

The invention discloses an NAND Flash bit error rate prediction method based on a support vector regression method. According to the characteristic that the data residence time and the P / E period number in the NAND Flash chip greatly influence the bit error rate, and a support vector regression has small samples, and the accurability is high, a manual wear experiment is carried out on the chip toobtain data, Existing data is used to establish a three-dimensional model among the bit error rate, the data residence time and the P / E cycle number, Therefore, the bit error rate of the chip is predicted to guide the adaptation of the error correction algorithm and improve the storage reliability of the data.; Compared with a traditional bit error rate prediction method based on a neural networkmethod, the bit error rate prediction method based on the support vector regression method has the advantages that under the condition that the accuracy is the same, the efficiency is improved by morethan five times.

Description

technical field [0001] The invention relates to the technical field of solid-state storage, and more specifically relates to a NAND Flash bit error rate prediction method based on a support vector regression method. Background technique [0002] At present, with the continuous improvement of Flash technology, NAND Flash has developed rapidly due to its unique characteristics such as high density, large capacity, low power consumption, non-volatile data, and fast I / O response, and has gradually become a high-speed, large-capacity The main storage medium of the storage system, thanks to the rapid improvement of the global semiconductor production process, the feature size of NAND Flash is shrinking, and its storage density is increasing. However, while reducing the unit storage cost, its storage reliability is sacrificed. The reduction in size leads to a smaller interval between the threshold voltages of adjacent cells in NAND Flash. During data access, memory cells are extrem...

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Problems solved by technology

[0002] At present, with the continuous improvement of Flash technology, NAND Flash has developed rapidly due to its unique characteristics such as high density, large capacity, low power consumption, non-volatile data, and fast I / O response, and has gradually become a high-speed, large-capacity The main storage medium of the storage system, thanks to the rapid improvement of the global semiconductor production process, the feature size of NAND Flash is shrinking, and its storage density is increasing. However, while reducing the unit storage cost, its storage reliability is sacrificed. The reduction in size leads to a smaller interval between the threshold voltages of adjacent cells in NAND Flash. During data access, memory cells are extremely susceptible to interference, which makes their storage reliability continue to decrease, especially as MLC (Multi-Level Cell) and TLC With the emergence of (Trinary-Level Cell) chips, the instability of NAND Flash is more obvious

[0003] In order to ensure the reliability of the data stored in NAND Flash, it is necessary to adapt various error correction codes with different error correction capabilities for NAND Flash, and the specific error correction code used depends on the accurate grasp of the bit error rate of Flash, and NAND Flash is put into application In the early stage, because the characteristics of the oxide layer are stable, there will generally not be serious errors. However, as the number of P / E cycles in the use of NAND Flash continues to increase, the probability of errors will increase approximately exponentially.

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